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charger assp flash mcu HT45F5R revision: v1.10 date: de ? e ?? e ? 1 ?? ? 01 ? de ? e ?? e ? 1 ?? ? 01 ?
rev. 1.10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ? de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu table of contents eates cpu featu ? es ......................................................................................................................... ? pe ? iphe ? al featu ? es ................................................................................................................. 7 gene?al des??iption ........................................................................................ 8 blo?k diag?a? .................................................................................................. 8 pin assign?ent ........... ..................................................................................... 9 pin des??iption .......... .................................................................................... 10 a?solute maxi?u? ratings .......................................................................... 1? d.c. cha?a?te?isti?s ....................................................................................... 1? a.c. cha?a?te?isti?s ....................................................................................... 14 a/d conve?te? ele?t?i?al cha?a?te?isti?s ........... ......................................... 15 lvd&lvr ele?t?i?al cha?a?te?isti?s ............................................................ 15 refe?en?e voltage cha?a?te?isti?s ........... .................................................... 1? lcd ele?t?i?al cha?a?te?isti?s ..................................................................... 1? dac ele?t?i?al cha?a?te?isti?s ... .................................................................. 1? opa cha?a?te?isti?s ...................................................................................... 1? ovp ele?t?i?al cha?a?te?isti?s ..................................................................... 17 ocp ele?t?i?al cha?a?te?isti?s ..................................................................... 17 powe? good cha?a?te?isti?s ........... .............................................................. 17 usb auto dete?to? ele?t?i?al cha?a?te?isti?s ........... .................................. 18 powe? on reset ele?t?i?al cha?a?te?isti?s .................................................. 19 syste? a??hite?tu?e ...................................................................................... ?0 clo ? king and pipelining ......................................................................................................... ? 0 p ? og ? a ? counte ? ................................................................................................................... ? 1 sta ? k ..................................................................................................................................... ?? a ? ith ? eti ? and logi ? unit C alu ........................................................................................... ?? flash p?og?a? me?o?y ................................................................................. ?? st ? u ? tu ? e ................................................................................................................................ ?? spe ? ial ve ? to ? s ..................................................................................................................... ?? look-up ta ? le ............. ........................................................................................................... ?? ta ? le p ? og ? a ? exa ? ple ........................................................................................................ ? 4 in ci ?? uit p ? og ? a ?? ing C icp ............................................................................................... ? 5 on-chip de ? ug suppo ? t C ocds ......................................................................................... ?? ram data me?o?y ......................................................................................... ?7 st ? u ? tu ? e ................................................................................................................................ ? 7 gene ? al pu ? pose data me ? o ? y ............................................................................................ ? 7 spe ? ial pu ? pose data me ? o ? y ............................................................................................. ? 8
rev. 1.10 ? de?e??e? 1?? ?01? rev. 1.10 ? de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu special function register description ........................................................ 29 indi ? e ? t add ? essing registe ? s C iar0 ? iar1 ......................................................................... ? 9 me ? o ? y pointe ? s C mp0 ? mp1 .............................................................................................. ? 9 bank pointe ? C bp ................................................................................................................. ? 0 a ?? u ? ulato ? C acc ............................................................................................................... ? 0 p ? og ? a ? counte ? low registe ? C pcl .................................................................................. ? 0 look-up ta ? le registe ? s C tblp ? tbhp ? tblh ..................................................................... ? 0 status registe ? C status .................................................................................................... ? 1 eeprom data memory ........... ....................................................................... 33 eeprom data me ? o ? y st ? u ? tu ? e ........................................................................................ ?? eeprom registe ? s ............ .................................................................................................. ?? reading data f ? o ? the eeprom ........................................................................................ ? 5 w ? iting data to the eeprom ................................................................................................ ? 5 w ? ite p ? ote ? tion ..................................................................................................................... ? 5 eeprom inte ?? upt ............. ................................................................................................... ? 5 p ? og ? a ?? ing conside ? ations ............. ................................................................................... ?? oscillators .......... ............................................................................................ 37 os ? illato ? ove ? view ............. .................................................................................................. ? 7 system clock confgurations ................................................................................................ ? 7 inte ? nal rc os ? illato ? C hirc ............. .................................................................................. ? 8 inte ? nal ?? khz os ? illato ? C lirc ........................................................................................... ? 8 supple ? enta ? y os ? illato ? ...................................................................................................... ? 8 operating modes and system clocks ......................................................... 38 syste ? clo ? ks ...................................................................................................................... ? 8 syste ? ope ? ation modes ...................................................................................................... 40 cont ? ol registe ? .................................................................................................................... 41 ope ? ating mode swit ? hing ................................................................................................... 4 ? stand ? y cu ?? ent conside ? ations ........................................................................................... 4 ? wake-up ................................................................................................................................ 4 ? watchdog timer ........... .................................................................................. 47 wat ? hdog ti ? e ? clo ? k sou ?? e .............................................................................................. 47 wat ? hdog ti ? e ? cont ? ol registe ? ............. ............................................................................ 47 wat ? hdog ti ? e ? ope ? ation ................................................................................................... 48 reset and initialisation .................................................................................. 49 reset fun ? tions ............. ....................................................................................................... 49 reset initial conditions ......................................................................................................... 51 input/output ports ......................................................................................... 54 pull-high resisto ? s ................................................................................................................ 54 po ? t a wake-up ............. ........................................................................................................ 55 i/o po ? t cont ? ol registe ? s ..................................................................................................... 55 i/o po ? t sou ?? e cu ?? ent cont ? ol ............................................................................................ 5 ? pin-sha ? ed fun ? tions ............. ............................................................................................... 57 pin-sha ? ed fun ? tion sele ? tion registe ? s ............. ................................................................. 57 i/o pin st ? u ? tu ? es .................................................................................................................. ? 0 p ? og ? a ?? ing conside ? ations ............. ................................................................................... ? 0
rev. 1.10 4 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 5 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu timer module C tm ........................................................................................ 61 int ? odu ? tion ........................................................................................................................... ? 1 tm ope ? ation ............. ........................................................................................................... ? 1 tm clo ? k sou ?? e ............. ...................................................................................................... ? 1 tm inte ?? upts ......................................................................................................................... ?? tm exte ? nal pins .................................................................................................................. ?? tm input/output pin sele ? tion .............................................................................................. ?? p ? og ? a ?? ing conside ? ations ............. ................................................................................... ?? standard type tm C stm .......... .................................................................... 64 standa ? d tm ope ? ation ............. ............................................................................................ ? 4 standa ? d type tm registe ? des ?? iption ............................................................................... ? 4 standa ? d type tm ope ? ating modes .................................................................................... ? 8 periodic type tm C ptm ............................................................................... 78 pe ? iodi ? tm ope ? ation ............. ............................................................................................ 78 pe ? iodi ? type tm registe ? des ?? iption ................................................................................ 78 pe ? iodi ? type tm ope ? ating modes ..................................................................................... 8 ? analog to digital converter .......... ................................................................ 91 a/d conve ? te ? ove ? view ....................................................................................................... 91 a/d conve ? te ? registe ? des ?? iption ...................................................................................... 9 ? a/d conve ? te ? ope ? ation ....................................................................................................... 94 a/d conve ? te ? refe ? en ? e voltage ......................................................................................... 95 a/d conve ? te ? input signals .................................................................................................. 95 conve ? sion rate and ti ? ing diag ? a ? .................................................................................. 9 ? su ?? a ? y of a/d conve ? sion steps ............. .......................................................................... 97 p ? og ? a ?? ing conside ? ations ............. ................................................................................... 98 a/d conve ? sion fun ? tion ............. ......................................................................................... 98 a/d conve ? sion p ? og ? a ?? ing exa ? ples ............. ................................................................. 99 usb auto detection ..................................................................................... 101 usb auto dete ? tion ........................................................................................................... 101 usb auto dete ? tion registe ? s ............. ............................................................................... 10 ? battery charge module .......... ..................................................................... 103 batte ? y cha ? ging constant cu ?? ent and constant voltage modes ...................................... 104 ocp and ovp fun ? tions .................................................................................................... 104 batte ? y cha ? ge module registe ? s ....................................................................................... 105 digital to analog conve ? te ? ................................................................................................. 105 operational amplifer 0 ........................................................................................................ 10 ? scom function for lcd .............................................................................. 108 lcd ope ? ation ............. ....................................................................................................... 108 lcd bias cu ?? ent cont ? ol ................................................................................................... 108 interrupts ...................................................................................................... 109 inte ?? upt registe ? s ............................................................................................................... 109 inte ?? upt ope ? ation ............................................................................................................... 11 ? exte ? nal inte ?? upt ............. ..................................................................................................... 115 ocvp inte ?? upt ............. ........................................................................................................ 115
rev. 1.10 4 de?e??e? 1?? ?01? rev. 1.10 5 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu ti ? e base inte ?? upts ............................................................................................................ 115 a/d conve ? te ? inte ?? upt ........................................................................................................ 11 ? lvd inte ?? upt ........................................................................................................................ 117 ee prom inte ?? upt ............. .................................................................................................. 117 multi-fun ? tion inte ?? upts ............. ........................................................................................... 117 tm inte ?? upts ........................................................................................................................ 117 inte ?? upt wake-up fun ? tion .................................................................................................. 118 p ? og ? a ?? ing conside ? ations ............. .................................................................................. 118 low voltage detector C lvd .......... .............................................................. 119 lvd registe ? ............. ........................................................................................................... 119 lvd ope ? ation ..................................................................................................................... 1 ? 0 application circuits ........... .......................................................................... 121 instruction set .............................................................................................. 122 int ? odu ? tion ......................................................................................................................... 1 ?? inst ? u ? tion ti ? ing ................................................................................................................ 1 ?? moving and t ? ansfe ?? ing data ............................................................................................. 1 ?? a ? ith ? eti ? ope ? ations .......................................................................................................... 1 ?? logi ? al and rotate ope ? ation ............................................................................................. 1 ?? b ? an ? hes and cont ? ol t ? ansfe ? ........................................................................................... 1 ?? bit ope ? ations ..................................................................................................................... 1 ?? ta ? le read ope ? ations ....................................................................................................... 1 ?? othe ? ope ? ations ............. .................................................................................................... 1 ?? instruction set summary .......... .................................................................. 124 ta ? le conventions ............................................................................................................... 1 ? 4 instruction defnition ................................................................................... 126 package information ................................................................................... 135 ? 4 -pin ssop (150 ? il) outline di ? ensions ......................................................................... 1 ?? ? 8-pin ssop (150 ? il) outline di ? ensions ......................................................................... 1 ? 7
rev. 1.10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 7 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu features cpu features ? operating v oltage: f sys =8mhz: 2.2v~5.5v ? up to 0.5s instruction cycle with 8mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? two oscillators: internal rc C hirc internal 32khz C lirc ? fully intergrated internal 8mhz oscillator requires no external components ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? 8-level subroutine nesting ? bit manipulation instruction
rev. 1.10 ? de?e??e? 1?? ?01? rev. 1.10 7 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu peripheral features ? flash program memory: 4k16 ? ram data memory: 1288 ? true eeprom memory: 648 ? watchdog t imer function ? 20 bidirectional i/o lines ? programmable i/o port source current for led driving ? software controlled 4-scom lines lcd driver with 1/2 bias ? two external interrupt lines shared with i/o pins ? multiple t imer modules for time measure, compare match output, capture input, pwm output, single pulse output functions ? dual t ime-base functions for generation of fxed time interrupt signals ? 8 external channels 12-bit resolution a/d converter ? usb auto detector for qc 2.0 ? battery charge module pgd(power good detector) dual operational amplifer functions for current sense ocp and ovp functions 12-bit dac ? low voltage reset function ? low voltage detect function ? flash program memory can be re-programmed up to 100,000 times ? flash program memory data retention > 10 years ? true eeprom data memory can be re-programmed up to 1,000,000 times ? true eeprom data memory data retention > 10 years ? package types: 24/28-pin ssop
rev. 1.10 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 9 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu general description the HT45F5R is an assp mcu specifically designed for b attery c harger applications. of fering users t he c onvenience of fl ash me mory m ulti-programming fe atures, t he de vice a lso i ncludes a wide range of functions and features. other memory includes an area of ram data memory as well as an area of true eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. the device includes an integrated multi-channel 12-bit a/d converter and an lcd driver . multiple and extremely flexible t imer m odules provide timing, puls e generation, capture input, compare match out put, si ngle pul se out put a nd pw m ge neration func tions. prot ective fe atures suc h a s a n internal w atchdog t imer and low v oltage reset and low v oltage detector coupled with excellent noise imm unity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of high speed and low speed internal oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the ability to operate and switch dynamically between a range of operating modes using dif ferent clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. this device conta ins a programmab le i/o port source current function which is used to implement led driving function. also the incl usion of fexible i/o programming features, t ime-base functions along with a range of circuit functions for battery char ge implementation, further enhance device functionality and fexibility for wide range of application possibilities. block diagram 8-?it risc mcu co?e flash p?og?a? me?o?y eeprom data me?o?y flash/eeprom p?og?a??ing ci??uit?y ram data me?o?y ti?e bases scom i/o low voltage dete?t wat?hdog ti?e? inte??upt cont?olle? reset ci??uit inte?nal rc os?illato?s 1?-?it a/d conve?te? ove? cu??ent p?ote?tion low voltage reset batte?y cha?ge? module ove? voltage p?ote?tion ti?e? modules usb auto dete?to? (qc?.0)
rev. 1.10 8 de?e??e? 1?? ?01? rev. 1.10 9 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu pin assignment pa1/an0/d+ pa?/an1/ocdsck/icpck ?4 ?? ?? ?1 ?0 19 18 17 1? 15 14 1? 1 ? ? 4 5 ? 7 8 9 10 11 1? pa5/an4/stck pa?/int0/an5/stpi a1x sensein a1n pa7/an?/a1p cp0n vdd/avdd vsense vss/avss isense pa4/an?/stp pb?/ptp0b pb?/ptp0 pb1/ptp0i pb5/scom1 pb?/scom? pb7/scom? pb4/scom0/ptp1 pb0/ptck0/int1 pa?/an?/d- pa0/vref/ocdsda/icpda HT45F5R/ht45v5r 24 ssop-a ?8 ?7 ?? ?5 ?4 ?? ?? ?1 ?0 19 18 17 1? 15 1 ? ? 4 5 ? 7 8 9 10 11 1? 1? 14 pa5/an4/stck pa?/int0/an5/stpi pa?/an1/ocdsck/icpck a1x sensein a1n pa7/an?/a1p cp0n pa0/vref/ocdsda/icpda vdd/avdd vsense pa?/an?/d- pa1/an0/d+ vss/avss isense pa4/an?/stp pb?/ptp0b pb?/ptp0 pb0/ptck0/int1 pb1/ptp0i pc0 pb4/scom0/ptp1 pb5/scom1 pb?/scom? pb7/scom? pc1/ptp1i pc?/ptp1b pc?/ptck1 HT45F5R/ht45v5r 28 ssop-a note : 1. if the pin-shared pin functions have multiple outputs simultaneously , the desired pin-shared function is determined by the corresponding software control bits. 2. the actual device and its equival ent ocds ev device share the same package type, however the ocds ev device part number is ht45v5r. pins ocdsck and ocdsda which are pin-shared with p a2 and pa0 are only used for the ocds ev device.
rev. 1.10 10 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 11 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu pin description with the exception of the power pins and some relevant transformer control pins, all pins on this device can be referenced by their port name, e.g. p a0, p a1 etc, which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the analog to digital converter, t imer module pins etc. t he function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. as the pin description table shows the situation for the package with the most pins, not all pins in the table will be available on smaller package sizes. pin name function op i/t o/t description pa0/vref/ ocdsda/icpda pa0 pawu papu pas0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high and wake-up. vref pas0 an adc ? efe ? en ? e voltage input ocdsda st cmos ocds add ? ess/data line ? fo ? ev ? hip only. icpda st cmos icp add ? ess/data line pa1/an0/d+ pa1 pawu papu pas0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high and wake-up. an0 pas0 an adc input ? hannel d+ pas0 an dac0 output pa ? /an1/ ocdsck/ icpck pa ? pawu papu pas0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high and wake-up. an1 pas0 an adc input ? hannel ocdsck st ocds ? lo ? k line ? fo ? ev ? hip only. icpck st icp ? lo ? k line pa ? /an ? /d- pa ? pawu papu pas0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high and wake-up. an ? pas0 an adc input ? hannel d- pas0 an dac1 output pa4/an ? /stp pa4 pawu papu pas1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high and wake-up. an ? pas1 an adc input ? hannel stp pas1 cmos stm output pa5/an4/stck pa5 pawu papu pas1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high and wake-up. an4 pas1 an adc input ? hannel stck pas1 st stm ? lo ? k input pa ? /int0/an5/ stpi pa ? pawu papu pas1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high and wake-up. int0 pas1 integ intc0 st exte ? nal inte ?? upt input an5 pas1 an adc input ? hannel stpi pas1 st stm ? aptu ? e input
rev. 1.10 10 de?e??e? 1?? ?01? rev. 1.10 11 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu pin name function op i/t o/t description pa7/an ? /a1p pa7 pawu papu pas1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high and wake-up. an ? pas1 an adc input ? hannel a1p pas1 st opa1 positive exte ? nal input pin pb0/ptck0/ int1 pb0 pbpu pbs0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. ptck0 pbs0 st ptm0 ? lo ? k input int1 pbs0 integ intc ? st exte ? nal inte ?? upt input pb1/ptp0i pb1 pbpu pbs0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. ptp0i pbs0 st ptm0 ? aptu ? e input pb ? /ptp0 pb ? pbpu pbs0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. ptp0 pbs0 cmos ptm0 output pb ? /ptp0b pb ? pbpu pbs0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. ptp0b pbs0 cmos ptm0 inve ? ted output pb4/scom0/ ptp1 pb4 pbpu pbs1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. scom0 scomc pbs1 scom softwa ? e ? ont ? olled lcd ? o ?? on output ptp1 pbs1 cmos ptm1 output pb5/scom1 pb5 pbpu pbs1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. scom1 scomc pbs1 scom softwa ? e ? ont ? olled lcd ? o ?? on output pb ? /scom ? pb ? pbpu pbs1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. scom ? scomc pbs1 scom softwa ? e ? ont ? olled lcd ? o ?? on output pb7/scom ? pb7 pbpu pbs1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. scom ? scomc pbs1 scom softwa ? e ? ont ? olled lcd ? o ?? on output pc0 pc0 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. pc1/ptp1i pc1 pcpu pcs0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. ptp1i pcs0 st ptm1 ? aptu ? e input pc ? /ptp1b pc ? pcpu pcs0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. ptp1b pcs0 cmos ptm1 inve ? ted output pc ? /ptck1 pc ? pcpu pcs0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. ptck1 pcs0 st ptm1 ? lo ? k input a1x a1x an opa1 output a1n a1n an opa1 negative input sensein sensein an opa1 signal input isense isense an cu ?? ent sense input vsense vsense an voltage sense input
rev. 1.10 1 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1? de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu pin name function op i/t o/t description cp0n cp0n an cmp0 negative input vdd/avdd vdd pwr digital positive powe ? supply avdd pwr analog positive powe ? supply vss/avss vss pwr digital negative powe ? supply avss pwr analog negative powe ? supply lenged: i/t: input type; o/t: output type; op: optional by register option; pwr: power; st: schmitt t rigger input; cmos: cmos output ; an: analog signal; *: v dd is the device pow er s upply w hile a vdd is the a dc pow er s upply. the a vdd pin is bonded together internally with vdd. **: vss is the device ground pin while a vss is the adc ground pin. the a vss pin is bonded together internally with vss. absolute maximum ratings supply v oltage .............. .................................................................................. v ss ?0.3v to v ss +6.0v input v oltage .............. .................................................................................... v ss ? 0.3v to v dd +0.3v storage t emperature ............... ..................................................................................... -50? c to 125?c operating t emperature .............. .................................................................................... -40? c to 85 ?c i ol t otal .............. ................................................................................................... .................... 80ma i oh t otal .............. ...................................................................................................................... -80ma total power dissipation .............. ........................................................................................... 500mw note: these are stress ratings only . stresses exceeding the range specified under "absolute maximum rating s" may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability.
rev. 1.10 1? de?e??e? 1?? ?01? rev. 1.10 1 ? de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu d.c. characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope ? ating voltage (hirc) f sys =f hirc =8mhz ? . ? 5.5 v i dd ope ? ating cu ?? ent (hirc) ? v no load ? all pe ? iphe ? als off ? wdt ena ? le ? lvr ena ? le ? opa ena ? le ? ocp/ovp ena ? le ? f sys =f hirc =8mhz 0.8 ? .0 ? a 5v 1.5 ? .0 ? a ope ? ating cu ?? ent (lirc) ? v no load ? all pe ? iphe ? als off ? opa ena ? le ? ocp/ovp ena ? le ? f sys =f lirc = ?? khz 0. ? 5 1. ? ? a 5v 0.5 ? 1. ? ? a i stb stand ? y cu ?? ent (idle0 mode ? lirc on) 5v no load ? adc off ? wdt ena ? le ? lvr disa ? le ? opa ena ? le ? ocp/ovp ena ? le 0.47 1.0 ? a stand ? y cu ?? ent (idle1 mode ? hirc) 5v no load ? adc off ? wdt ena ? le ? f sys =8mhz on ? opa ena ? le ? ocp/ovp ena ? le 0.89 ? .0 ? a stand ? y cu ?? ent (sleep0 mode ? lirc off) 5v no load ? adc off ? wdt disa ? le ? lvr disa ? le ? opa ena ? le ? ocp/ovp ena ? le 0.4 ? 1.0 ? a stand ? y cu ?? ent (sleep1 mode ? lirc on) 5v no load ? adc off ? wdt ena ? le ? lvr disa ? le ? opa ena ? le ? ocp/ovp ena ? le 0.47 1.0 ? a v il input low voltage fo ? i/o po ? ts 5v 0 1.5 v 0 0. ? v dd v v ih input high voltage fo ? i/o po ? ts 5v ? .5 5 v 0.8v dd v dd v i ol sink cu ?? ent fo ? i/o po ? t ? v v ol =0.1v dd 15.5 ? 1 ? a 5v v ol =0.1v dd ? 1 ?? ? a i oh sou ?? e cu ?? ent fo ? i/o po ? ts ? v v oh =0.9v dd ? sledcn[ ? +1 ? ? ] = 00b (n=0 ? 1 ? ? =0 o ? ? o ? 4 o ? ? ) -0.7 -1.4 ? a 5v v oh =0.9v dd ? sledcn[ ? +1 ? ? ] = 00b (n=0 ? 1 ? ? =0 o ? ? o ? 4 o ? ? ) -1.4 - ? .8 ? a ? v v oh =0.9v dd ? sledcn[ ? +1 ? ? ] = 01b (n=0 ? 1 ? ? =0 o ? ? o ? 4 o ? ? ) -1. ? - ? .4 ? a 5v v oh =0.9v dd ? sledcn[ ? +1 ? ? ] = 01b (n=0 ? 1 ? ? =0 o ? ? o ? 4 o ? ? ) - ? .5 -5.0 ? a ? v v oh =0.9v dd ? sledcn[ ? +1 ? ? ] = 10b (n=0 ? 1 ? ? =0 o ? ? o ? 4 o ? ? ) -1.7 - ? .5 ? a 5v v oh =0.9v dd ? sledcn[ ? +1 ? ? ] = 10b (n=0 ? 1 ? ? =0 o ? ? o ? 4 o ? ? ) - ? .5 -7.0 ? a ? v v oh =0.9v dd ? sledcn[ ? +1 ? ? ] = 11b (n=0 ? 1 ? ? =0 o ? ? o ? 4 o ? ? ) - ? .5 -7.0 ? a 5v v oh =0.9v dd ? sledcn[ ? +1 ? ? ] = 11b (n=0 ? 1 ? ? =0 o ? ? o ? 4 o ? ? ) -7. ? -14.5 ? a r ph pull-high resistan ? e fo ? i/o po ? ts ? v ? 0 ? 0 100 k 5v 10 ? 0 50 k i leak input leakage cu ?? ent 5v v in =v dd o ? v in =v ss 1 a
rev. 1.10 14 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 15 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu a.c. characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd condition f sys syste ? clo ? k (hirc) ? .4v ~ 5.5v f sys =f hirc =8mhz 8 mhz syste ? clo ? k (lirc) ? . ? v ~ 5.5v f sys =f lirc = ?? khz ?? khz f hir c high speed inte ? nal rc os ? illato ? (hirc) ? v/5v ta= ? 5c - ? % 8 + ? % mhz ? v/5v ta=0c ~ 70c - 5% 8 + 5% mhz ? . ? v ~ 5.5v ta=0c ~ 70c - 8% 8 + 8% mhz ? . ? v ~ 5.5v ta= -40c ~ 85c - 1 ? % 8 + 1 ? % mhz f lirc low speed inte ? nal rc os ? illato ? (lirc) ? . ? v ~ 5.5v ta= -40c ~ 85c 4 ?? 80 khz t rstd syste ? reset delay ti ? e (por reset ? lvr ha ? dwa ? e reset ? wdt softwa ? e reset) 10 50 100 ? s syste ? reset delay ti ? e (wdt ti ? e-out ha ? dwa ? e cold reset) 10 1 ? .7 50 ? s t sst syste ? sta ? t-up ti ? e ? pe ? iod (wake-up f ? o ? powe ? down mode and f sys off) f sys =f h ~ f h / ? 4 ? f h =f hirc 1 ? t hirc f sys =f sub =f lirc ? t lirc syste ? sta ? t-up ti ? e ? pe ? iod (wake-up f ? o ? powe ? down mode and f sys on) f sys =f lirc ? t sys t int exte ? nal inte ?? upt mini ? u ? pulse width 0. ? s t eerd eeprom read ti ? e ? 5 t sys t eewr eeprom w ? ite ti ? e ? 7 ? s t tck stck and ptckn pin mini ? u ? pulse width 0. ? s t tpi stpi and ptpni pin mini ? u ? pulse width 0. ? s note 1. t sys i sys dd h dud i h hudo oodu iuhth d ghso dsdu og h hhg hhh 9 dg 9 dg odhg d oh h ghyh d soh
rev. 1.10 14 de?e??e? 1?? ?01? rev. 1.10 15 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu a/d converter electrical characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope ? ating voltage ? .7 5.5 v v adi input voltage 0 v ref v v ref refe ? en ? e voltage ? v dd v dnl diffe ? ential nonlinea ? ity ? v v ref =v dd ? t adck =0.5s ? lsb 5v v ref =v dd ? t adck =0.5s ? v v ref =v dd ? t adck =10s 5v v ref =v dd ? t adck =10s inl integ ? al nonlinea ? ity ? v v ref =v dd ? t adck =0.5s 4 lsb 5v v ref =v dd ? t adck =0.5s ? v v ref =v dd ? t adck =10s 5v v ref =v dd ? t adck =10s i adc additional cu ?? ent fo ? adc ena ? le ? v no load (t adck =0.5s) 1 ? ? a 5v no load (t adck =0.5s) 1.5 ? ? a t adck clo ? k pe ? iod 0.5 10 s t on ? st adc on to adc sta ? t 4 s t ads sa ? pling ti ? e 4 t adck t adc conve ? sion ti ? e (in ? lude adc sa ? ple and hold ti ? e) 1 ? t adck lvd&lvr electrical characteristics ta= ? 5 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope ? ating voltage v lvr 5.5 v v lvr low voltage reset voltage lvr ena ? le - 5% ? .1 + 5% v v lvd low voltage dete ? tion voltage lvd ena ? le ? voltage sele ? t ? .0v - 5% ? .0 + 5% v lvd ena ? le ? voltage sele ? t ? . ? v - 5% ? . ? + 5% lvd ena ? le ? voltage sele ? t ? .4v - 5% ? .4 + 5% lvd ena ? le ? voltage sele ? t ? .7v - 5% ? .7 + 5% lvd ena ? le ? voltage sele ? t ? .0v - 5% ? .0 + 5% lvd ena ? le ? voltage sele ? t ? . ? v . - 5% ? . ? + 5% lvd ena ? le ? voltage sele ? t ? . ? v - 5% ? . ? + 5% lvd ena ? le ? voltage sele ? t 4.0v - 5% 4.0 + 5% i op ope ? ating cu ?? ent 5v lvd ena ? le ? lvr ena ? le ? vbgen=0 ? 0 ? 5 a 5v lvd ena ? le ? lvr ena ? le ? vbgen=1 ? 00 ? 00 a t lvds lvdo sta ? leti ? e fo ? lvr ena ? le ? vbgen=0 ? lvd off on 15 s fo ? lvr disa ? le ? vbgen=0 ? lvd off on 150 s t lvr mini ? u ? low voltage width to reset ? 8 500 ? 40 s
rev. 1.10 1 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 17 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu reference voltage characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v bg bandgap refe ? en ? e voltage - 5% 1.09 + 5% v t bgs vbg tu ? n on sta ? le ti ? e 150 s note the v bg yodh hg d h yhuhu hudo do s lcd electrical characteristics symbol parameter test conditions min. typ. max. unit v dd conditions i bias v dd / ? ? ias ? u ?? ent fo ? lcd 5v isel[1:0]=00b 17.5 ? 5 ?? .5 a 5v isel[1:0]=01b ? 5 50 ? 5 a 5v isel[1:0]=10b 70 100 1 ? 0 a 5v isel[1:0]=11b 140 ? 00 ?? 0 a v scom v dd / ? voltage fo ? lcd com po ? t ? . ? v~5.5v no load 0.475 v dd 0.5 v dd 0.5 ? 5 v dd v dac electrical characteristics ta= ? 5 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope ? ating voltage ? . ? 5.5 v v daco output voltage range v ss v dd v i dac additional cu ?? ent fo ? dac ena ? le 5v 500 ? 00 a note dac v oltage formula (d110/2 12 ) 9 dd opa characteristics ta= ? 5 c symbol parameter test conditions min. typ. max. unit v dd conditions d.c. characteristics v dd ope ? ating voltage ? . ? 5.5 v v os input offset voltage 5v without ? ali ?? ation (a0of[4:0]=10000b) -15 15 ? v 5v with ? ali ?? ation -4 +4 ? v v cm co ?? on mode voltage range 5v v ss v dd -1.4 v i source output cu ?? ent 5v inp=1v ? inn=0v ? v out =4.5v ? 5 ? a i sink inp=0v ? inn=1v ? v out =0.5v 5 7 ? a a.c. characteristics a ol open loop gain 5v ? 0 80 db sr slew rate 5v no load 0. ? v/s gbw gain bandwidth 5v v cm =v dd -1.4 ? r l =1m, c l =100pf 1 ? mhz
rev. 1.10 1? de?e??e? 1?? ?01? rev. 1.10 17 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu ovp electrical characteristics ta= ? 5 c symbol parameter test conditions min. typ. max. unit v dd conditions v ddc ovp ope ? ating voltage 4. ? 5.5 v i ddc ovp ope ? ating cu ?? ent 5v ?? 5 a v hys hyste ? esis width ? 0 40 ? 0 ? v v cm input co ?? on mode range v ss v dd -1.4 v a ol co ? pa ? ato ? open loop gain ? 0 80 db ovpd vsense ove ? voltage dete ? tion 5v - ? % ? v + ? % v ovprs ovp response ti ? e 0. ? 5 8 ? s 1rwh 7kh ?9? prgxoh lv lqwhjudjh g zlwk d frpsdudwru dqg wkh lqwhuqd o 9 yrowdjh lv surylghg wr wkh frpsdudwru qhjdwlyh 7 kh ?9?' yh ulfdwlrq sxusrvh l v w kdw zkh q 9vh qvh l v p ruh w kdq 9 w kh f rpsdudwru rxw sxwv kljk ohyho rwkhuzlvh orz ohyho ocp electrical characteristics ta= ? 5 c symbol parameter test conditions min. typ. max. unit v dd conditions v ddc ocp ope ? ating voltage 4. ? 5.5 v i ddc co ? pa ? ato ? ope ? ating cu ?? ent 5v ? 00 a v cmpos co ? pa ? ato ? input offset voltage 5v -15 15 ? v v hys hyste ? esis width ? 0 40 ? 0 ? v v cm input co ?? on mode range v ss v dd -1.4 v a ol co ? pa ? ato ? open loop gain ? 0 80 db ocprs ocp response ti ? e v od =10 ? v ? c l = ? pf 0. ? 5 8 ? s power good characteristics ta= ? 5c symbol parameter test condition min. typ. max. unit v dd conditions v det dete ? tion voltage - ? % 4. ? v + ? % v i ddc powe ? good ope ? ating cu ?? ent 5v 85 a t pds powe ? good output sta ? le ti ? e 1 ? 5 ? 50 500 s
rev. 1.10 18 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 19 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu usb auto detector electrical characteristics ta= ? 5c symbol parameter test co nditions min. typ. max. unit v dd conditions v dac dac ope ? ation voltage ? . ? 5.5 v i dac dac ope ? ation cu ?? ent ? v no load 0. ? 0.9 ? a 5v no load 1.0 1.5 ? a i dacsd dac shutdown cu ?? ent no load 0.1 a n r dac resolution 8 ? its dnl dac diffe ? ential nonlinea ? ity no load ? dac ? efe ? en ? e=v dd 1 lsb inl dac integ ? al nonlinea ? ity no load ? dac ? efe ? en ? e=v dd ? lsb v daco output voltage range code=00h v ss v ss + 0. ? v code=0ffh v ref - 0. ? v ref v v ref refe ? en ? e voltage ? v dd v t st settling ti ? e ? v c load =50pf ? . ? s 5v c load =50pf ? . ? s r o r ? r output resisto ? ? v ? k 5v 5 k r on analog swit ? h on resistan ? e ? etween d+ and d- 5v ? 5 ? 5 r pl1 pull-low resistan ? e fo ? d+ ? .5v 700 1 ? 00 1850 k 5v 400 900 1400 k r pl ? pull-low resistan ? e fo ? d- ? .5v 15 ? 0 ?? k 5v 15 ? 0 ?? k err the e ?? o ? fo ? d+ ? d- output voltage 5v dac ? efe ? en ? e=v dd ? dac digital value=144 ? d+, d- connect 150k to ground ? .57 ? .7 ? .84 v 5v dac ? efe ? en ? e=v dd ? dac digital value=107 ? d+, d- connect 150k to ground 1.9 ? .0 ? .1 v r d the su ? of dx_r1 and dx_r ? ? v ? 4 ? k 5v ? 4 ? k rr d the ratio of dx_r1/dx_r ? ? v - ? % 1:1 + ? % 5v - ? % 1:1 + ? % v oh output high voltage fo ? i/o po ? ts ? v i oh = -7 ? a ? .7 v 5v i oh = -14 ? a 4.5 v v ol output low voltage fo ? i/o po ? ts ? v i ol = ? 1 ? a 0. ? v 5v i ol = ??? a 0.5 v
rev. 1.10 18 de?e??e? 1?? ?01? rev. 1.10 19 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu power on reset electrical characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd sta ? t voltage to ensu ? e powe ? -on reset 100 ? v rr por v dd rising rate to ensu ? e powe ? -on reset 0.0 ? 5 v/ ? s t por mini ? u ? ti ? e fo ? v dd stays at v por to ensu ? e powe ? -on reset 1 ? s v dd t por rr por v por ti?e
rev. 1.10 ? 0 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?1 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture . the device takes advantage of the usual features found within risc microcontrollers providing increased speed of operation and periodic performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or c all i nstructions. an 8-bi t wi de al u i s use d i n pra ctically a ll i nstruction se t ope rations, whi ch carries out arithme tic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the d ata m emory and can be directly or indirectly addressed. the simpl e addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d c ontrol system with m aximum reliability a nd fexibility. t his makes t he device suitable for l ow- cost, high-volume production for controller applications clocking and pipelining the main system clock, derived from either a hirc or lirc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. fet?h inst. (pc+?) exe?ute inst. (pc+1) os?illato? clo?k (syste? clo?k) phase clo?k t1 phase clo?k t? phase clo?k t? phase clo?k t4 p?og?a? counte? pipelining pc pc+1 pc+? fet?h inst. (pc+1) exe?ute inst. (pc) exe?ute inst. (pc-1) fet?h inst. (pc) system clock and pipelining
rev. 1.10 ?0 de?e??e? 1?? ?01? rev. 1.10 ? 1 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. exe?ute inst. 1 fet?h inst. ? 1 mov a? [1?h] ? call delay ? cpl [1?h] 4: 5: ? delay: nop fet?h inst. 1 exe?ute inst. ? fet?h inst. ? flush pipeline fet?h inst. ? exe?ute inst. ? fet?h inst. 7 instruction fetching program counter during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is e xecuted e xcept for i nstructions, suc h a s "jmp" or "cal l" t hat de mand a j ump t o a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter program counter high byte pcl register pc11~pc8 pcl7~pcl0 the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly, h owever, a s o nly t his l ow b yte is available for manipulation, the jum ps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?? de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is or ganized into 8 levels and neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily . however , when the stack is full, a call subroutine instruction can still be exec uted whic h wi ll result in a st ack overfow . prec autions should be ta ken to avoid such cases which might cause unpredictable program branching. if the stack is overfow , the frst program counter save in the stack will be lost. sta?k pointe? sta?k level ? sta?k level 1 sta?k level ? : : : sta?k level 8 p?og?a? me?o?y p?og?a? counte? botto? of sta?k arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation: rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement: inca, inc, deca, dec ? branch decision: jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu flash program memory the program memory is the location where the user code or program is stored. for this device the program memory are flash type, which means it can be programmed and re-programmed a l arge num ber of t imes, a llowing t he use r t he c onvenience of c ode m odification on t he sa me device. by using the appropriate programming tools, this flash device of fers users the fexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. structure the progra m me mory ha s a c apacity of 4k16 bi ts. t he progra m me mory i s a ddressed by t he program counter and also contains data, table information and interrupt entries. t able data, which can be setup in any location within the program memory , is addressed by a separate table pointer register. 000h initialisation ve?to? 004h 0fffh 1? ?its inte??upt ve?to?s 0?ch 0?0h program memory structure special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h i s re served fo r u se b y t his d evice re set fo r p rogram i nitialisation. aft er a d evice r eset i s initiated, the program will jump to this location and begin execution. look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp and tbhp . this register defnes the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the "t abrd [m]" or "t abrdl[m]" instructions, respectively . when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data me mory r egister [ m] a s sp ecified i n t he i nstruction. t he h igher o rder t able d ata b yte f rom the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as "0". the accompanying diagram illustrates the addressing data fow of the look-up table.
rev. 1.10 ? 4 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?5 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu last page o? tbhp registe? add?ess tblp registe? data 1? ?its p?og?a? me?o?y registe? tblh use? sele?ted registe? high byte low byte table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is "0f00h" which refers to the start address of the last page within the 4k words program memory of the device. the table pointer is setup here to have an initial value of "06h". this will ensure that the frst data read from the data table will be at the program memory address "0f06h" or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the specifc page if the "t abrd [m]" instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the "tabrd [m]" instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a mov a,0fh ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address "0f06h" transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdc tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address "0f05h" transferred to tempreg2 and tblh in this ; example the data "1ah" is transferred to tempreg1 and data "0fh" to ; register tempreg2 : : org 0f00h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
rev. 1.10 ?4 de?e??e? 1?? ?01? rev. 1.10 ? 5 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu in circuit programming C icp the provision of flash type program memory provides the user with a means of convenient and easy upgrades a nd m odifcations t o t heir p rograms o n t he sa me d evice. as a n a dditional c onvenience, holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the holtek flash mcu to w riter programming pin correspondence table is as follows: holtek writer pins mcu programming pins pin description icpda pa0 p ? og ? a ?? ing se ? ial data/add ? ess icpck pa ? p ? og ? a ?? ing clo ? k vdd vdd powe ? supply vss vss g ? ound the program memory and eeprom data memory can both be programmed serially in-circuit using this 4-wi re inte rface. dat a is downloaded and upl oaded serial ly on a single pin wit h an additi onal line for the clock. t wo additional lines are required for the power supply and ground. the technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. * * w?ite?_vdd icpda icpck w?ite?_vss to othe? ci??uit vdd pa0 pa? vss w?ite? conne?to? signals mcu p?og?a??ing pins note: * may be resistor or capacitor . the resistance of * must be greate r than 1k or the capacitance of * must be less than 1nf.
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?7 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu on-chip debug support C ocds there is an ev chip named ht45v5r which is used to emulate the HT45F5R device. this ev chip device also provides an "on-chip debug" function to debug the device during the development process. the ev chip and the actual mcu device are almost functionally compatible except for the " on-chip d ebug" function. u sers can us e the ev chip device to emulate the real chip device behavior by connecting the ocdsda and ocdsck pins to the holtek ht -ide development tools. the ocdsda pin is the ocds data/address input/output pin while the ocdsck pin is the ocds clock input pin. when users use the ev chip for debugging, other functions which are shared with the ocdsda and ocdsck pi ns in the actual mcu de vice will ha ve no ef fect in the ev chip. however, the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp . for a more detailed ocds description, refer to the corresponding document named "holtek e-link for 8-bit mcu ocds users guide". holtek e-link pins ev chip pins pin description ocdsda ocdsda on- ? hip de ? ug suppo ? t data/add ? ess input/output ocdsck ocdsck on- ? hip de ? ug suppo ? t clo ? k input vdd vdd powe ? supply gnd vss g ? ound
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 7 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two types, the frst of these is an area of ram, known as the special function data memory. he re a re l ocated r egisters wh ich a re n ecessary f or c orrect o peration o f t he d evice. ma ny of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory , which is reserved for general purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into two banks. the special purpose data memory registers addressed from 00h~7fh in data memory are common and accessible in bank 0 and the eec register at the address 40h in bank 1. switching between the dif ferent data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for the device is the address 00h. special purpose data memory general purpose data memory available banks banks capacity banks 0 ? 1 bank 0: 00h~7fh bank 1: 40h (eec) 1 ? 8 8 bank 0: 80h~ffh data memory summary 00h 80h ffh spe?ial pu?pose data me?o?y gene?al pu?pose data me?o?y bank 0 bank 1 40h 7fh data memory structure general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieve d for use later . it is this area of ram memory that is known as general purpose data memory . this area of data memory is fully accessible by the user programing for both reading and wr iting o perations. b y u sing t he b it o peration i nstructions i ndividual b its c an b e se t o r r eset under program control giving the user a lar ge range of fexibility for bit manipulation in the data memory.
rev. 1.10 ? 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?9 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only , the details of which are located under the relevant special function register section. note that for locat ions that are unused, any read instruction to these addresses will return the value "00h". bank 0 bank 1 : unused? ?ead as 00h 40h 41h 4?h 4?h eea eed ptm1c0 ptm1c1 44h ptm1dl 45h ptm1dh 4?h ptm1al 47h ptm1ah 48h ptm1rpl 49h ptm1rph 4ah 4bh 4ch 4dh 4eh 4fh sledc0 50h sledc1 51h aduda0 5?h 7fh aduda1 5?h aduc0 54h aduc1 55h dacl 5?h dach 57h 58h intc0 59h intc1 5ah intc1 5bh 5ch 00h 01h 0?h 0?h iar0 mp0 iar1 mp1 bp 04h acc 05h pcl 0?h tblp 07h tblh 08h tbhp 09h status 0ah lvdc 0bh integ 0ch scc 0dh hircc 0eh rstfc 0fh sadol 10h sadoh 11h sadc0 1?h sadc1 1?h pa 14h pac 15h papu 1?h pawu 17h pas0 18h pas1 19h wdtc 1ah pb 1bh pbc 1ch pbpu 1dh pbs0 1eh pbs1 1fh pc ?0h pcc ?1h pcpu ??h pcs0 ??h ?4h tbc ?5h scomc ??h stmc0 ?7h ?8h stmc1 ?9h stmdl ?ah stmdh ?bh stmal ?ch stmah ?dh chrgen ?eh ?fh dacc ?0h sensw a0vos pgdr ?1h ??h ??h mfi0 mfi1 mfi? ptm0c0 ptm0c1 ptm0dl ?4h ?5h ??h ?7h ?8h ?9h ?ah ptm0dh ptm0al ptm0ah ptm0rpl ptm0rph ?bh ?ch ?dh ?eh ?fh eec bank 0 bank 1 special purpose data memory
rev. 1.10 ?8 de?e??e? 1?? ?01? rev. 1.10 ? 9 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of "00h" and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two me mory po inters, k nown a s mp0 a nd mp1 a re p rovided. t hese me mory po inters a re physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the releva nt indirect addressing registers is carried out, the actual address that the microcontroller is di rected to is the address specifed by the relat ed memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according t o bp register. direct ad dressing c an only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org00h start : m ov a , 04h ; setup size of block m ov block , a m ov a , offset adres1 ; accumulator loaded with frst ram address m ov mp0 , a ; setup memory pointer with frst ram address loop : c lr iar0 ; clear the data at address defned by mp0 i nc mp0 ; increment memory pointer s dz block ; check if last memory location has been cleared jm p loop continue : the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses.
rev. 1.10 ? 0 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?1 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu bank pointer C bp for this device, the data memory is divided into two banks, bank0 and bank1. selecting the required data memory area is achieved using the bank pointer . bit 0 of the bank pointer is used to select data memory banks 0~1. the da ta me mory i s i nitialised t o ba nk 0 a fter a re set, e xcept for a w dt t ime-out re set i n t he power down mode, in which case, the data memory bank remains unaf fected. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. accessing data from bank1 must be implemented using indirect addressing. bp register bit 7 6 5 4 3 2 1 0 na ? e dmbp0 r/w r/w por 0 bit 7 ~ 1 unimplemented, read as "0" bit 0 dmbp0 : select data memory banks 0: bank 0 1: bank 1 accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user -defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nters a nd i ndicate t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the "inc" or "dec" instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 1.10 ?0 de?e??e? 1?? ?01? rev. 1.10 ? 1 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the "clr wdt" or "hal t" instruction. the pdf fag is af fected only by executing the "halt" or "clr wdt" instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the "clr wdt" instruction. pdf is set by executing the "halt" instruction. ? to is cleared by a system power-up or executing the "clr wdt" or "halt" instruction. t o is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?? de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu status register bit 7 6 5 4 3 2 1 0 na ? e to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 x x x x "x": unknown bit 7~6 unimplemented, read as "0" bit 5 to : w atchdog t ime-out fag 0: after power up or executing the "clr wdt" or "halt" instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu eeprom data memory this device contains an area of internal eeprom data memory . eeprom, which stands for electrically erasable programmable read only memory , is by its nature a non-volatile form of memory, with data retention even when its power supply is removed. by incorporating this kind of d ata m emory, a wh ole n ew h ost o f a pplication p ossibilities a re m ade a vailable t o t he d esigner. the a vailability o f e eprom st orage a llows i nformation su ch a s p roduct i dentifcation n umbers, calibration values , s pecifc us er data, s ystem s etup data or other product information to be s tored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is 648 bits for this device. unlike the program memory and ram data memory , the eeprom data memory is not directly mapped and is therefore not directly accessible in the same way as the other types of memory . read and w rite operations to the eeprom a re c arried o ut i n si ngle b yte o perations u sing a n a ddress r egister a nd a d ata r egister i n bank 0 and a single control register in bank 1. eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address registers, eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same way as any other special functi on regist er. the eec register however , be ing located in bank1, cannot be direct ly addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register , iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register , bp, set to the value, 01h, before any operations on the eec register are executed. register name bit 7 6 5 4 3 2 1 0 eea eea5 eea4 eea ? eea ? eea1 eea0 eed d7 d ? d5 d4 d ? d ? d1 d0 eec wren wr rden rd eeprom control registers list eea register bit 7 6 5 4 3 2 1 0 na ? e eea5 eea4 eea ? eea ? eea1 eea0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5~0 eea5~eea0 : eeprom address eeprom address bit 5 ~ bit 0
rev. 1.10 ? 4 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?5 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu eed register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : eeprom data eeprom data bit 7 ~ bit 0 eec register bit 7 6 5 4 3 2 1 0 na ? e wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as "0" bit 3 wren : eeprom w rite enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. bit 1 rden : eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero w ill inhibit d ata eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the applic ation program will activ ate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to "1" at the same time in one instruction. the wr and rd can not be set to "1" at the same time.
rev. 1.10 ?4 de?e??e? 1?? ?01? rev. 1.10 ? 5 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu reading data from the eeprom to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he rd bi t t o de termine whe n t he da ta i s valid for reading. writing data to the eeprom to write data to the eeprom, the eeprom address of the data to be written must frst be placed in t he ee a regist er and t he dat a pla ced in t he ee d regist er. then t he writ e enabl e bit , wren, in the eec register must first be set high to enable the write function. after this, the wr bit in the e ec r egister m ust b e i mmediately se t h igh t o i nitial a wr ite c ycle. t hese t wo i nstructions must be executed consecutively . the global interrupt bit emi should also first be cleared before implementing any write operations, and then set again after the write cycle has started. note that setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on t he w rite e nable b it i n t he c ontrol r egister wi ll b e c leared p reventing a ny wr ite operations. also at power -on the bank pointer , bp , will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the w rite enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must first be enabled by setting the dee bit in the relevant interrupt register . when an eeprom write cycle ends, the def request fag will be set. if the global, eeprom interrupt are enabled and the stack is not full, a subroutine call to the eeprom interrupt vector , will take place. when the eeprom interrupt is serviced, the eeprom interrupt fag def will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts.
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?7 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be periodic by ensuring that the w rite enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1where the eeprom control register exist. although certainly not necessary , consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. note that the device should not enter the id le or sleep mode until the eeprom read or write operation is totally complete. otherwise, the eeprom read or write operation will fail. programming examples ? reading data from the eeprom C polling method 029((3520b5(6 xvhughhgdgguhvv 029(( 029 vhwxsphprusrlwhu03 02903 03srlwvwr((&uhjlvwhu 029 vhwxsdn3rlwhu 0293 6(7,5 vhw5(1elwhdeohuhdgrshudwlrv 6(7,5 vwduw5hdg&fohvhw5elw back: 6,5 fkhfhdffhh -03. /5,5 ldeh3520lh /53 02 hhdddhlh 025b ? writing data to the eeprom C polling method 029((3520b5(6 xvhughhgdgguhvv 029(( 029((3520b7 xvhughhggdwd 029(( 029 vhwxsphprusrlwhu03 02903 03srlwvwr((&uhjlvwhu 029 vhwxsdn3rlwhu 0293 &/5 (0, 6(7,5 vhw:5(1elwhdeohzulwhrshudwlrv 6(7,5 vwduw:ulwh&fohvhw:5elwh[hfxwhglpphgldwhodiwhu h:51el 60, back: 6,5 fkhflhffhh -03. /5,5 ldeh3520lh /53
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 7 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu oscillators various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through relevant control registers. oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for t he w atchdog t imer a nd t ime b ase i nterrupts. t wo f ully i ntegrated i nternal o scillators, r equiring no extern al components, are provided to form a wide range of both fast and slow system oscillators. the h igher f requency o scillator p rovides h igher p erformance b ut c arry wi th i t t he d isadvantage o f higher power requirements, while the opposite is of course true for the lower frequency oscillator . with t he c apability of dyna mically swi tching be tween fa st a nd sl ow syst em c lock, t his de vice ha s the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. inte ? nal high speed rc hirc 8mhz inte ? nal low speed rc lirc ?? khz oscillator types system clock confgurations there are t wo m ethods of generat ing t he syst em cl ock, a high spee d osci llator and a l ow spee d oscillator. the high speed oscillator is the internal 8mhz rc oscillato r. the low speed oscillator is the intern al 32khz rc oscillator . selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the cks2 ~ cks0 bits in the scc register and as the system clock can be dynamically selected. hircen p?es?ale? f h high speed os?illato? low speed os?illato? f h /? f h /1? f h /?4 f h /8 f h /4 f h /?? cks?~ cks0 f sys f sub f sub lirc f lirc f lirc hirc f h idle0 sleep idle? sleep system clock confgurations
rev. 1.10 ? 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?9 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the i nternal r c o scillator h as a f ixed f requency o f 8 mhz. de vice t rimming d uring t he manufacturing process and the inclusion of internal frequency compensati on circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at temperature of 25 c degrees, the fxed oscillation frequency of the hirc will have a tolerance within 2%. internal 32khz oscillator C lirc the i nternal 3 2khz sy stem osc illator i s t he l ow f requency o scillator. i t i s a f ully i ntegrated rc osc illator wi th a t ypical fre quency of 32khz a t 5v , re quiring no e xternal c omponents for i ts implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. supplementary oscillator the low speed oscillator , in addition to providing a system clock source is also used to provide a c lock so urce t o t wo o ther d evice f unctions. t hese a re t he w atchdog t imer a nd t he t ime b ase interrupts. operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red port able a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided the device with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks this device has two dif ferent clock sources for both the cpu and peripheral function operation. by providing the user with clock selections using register programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency , f h , or a low frequency , f sub , and is se lected u sing t he c ks2~cks0 b its i n t he sc c r egister. t he h igh sp eed sy stem c lock c an b e sourced from hirc oscillator . the low speed system clock source can be sourced from the internal clock f sub . the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. there is one additional internal clock for the peripheral circuits, the t ime base clock, f tbc . f tbc i s sourced from the lirc oscillator . the f tbc clock is used as a source for the t ime base interrupt functions and for the tm.
rev. 1.10 ?8 de?e??e? 1?? ?01? rev. 1.10 ? 9 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu hircen p?es?ale? high speed os?illato? low speed os?illato? f h /? f h /1? f h /?4 f h /8 f h /4 f h /?? cks?~ cks0 f sys f sub f sub lirc f lirc f lirc hirc f h lvr wdt f lirc f sys /4 ti?e base 0 f tbc p?es?ale? 0 tb0 [?:0] tb1 [1:0] f sys /4 f tbc p?es?ale? 1 ti?e base 1 f tb f tb idle0 sleep idle? sleep device clock confgurations note: when the system clock source f sys is switched to f sub from f h , the high speed oscillator can be stopped to conserve the power or continue to oscillate to provide the clock source, f h ~f h /64, for peripheral circuit to use, which is determined by confguring the corresponding high speed oscillator enable control bit.
rev. 1.10 40 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 41 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu system operation modes there are six dif ferent modes of operation for the microcontroller , each one with its own special characteristics and which can be chosen according to the specifc performance and power requirements of the application. there are two modes allowing normal operation of the microcontroller , the normal mode and slow mode. the remaining four modes, the sleep , idle0, idle1 and idle2 mode are used when the microcontroller cpu is switched off to conserve power. operation mode cpu related register value f sys f h f sub f lirc fhiden fsiden cks[2:0] normal mode on x x 000~110 on on on on slow mode on x x 111 on on/off (1) on on idle0 mode off 0 1 000~110 off off on on 111 on idle1 mode off 1 1 xxx on on on on idle ? mode off 1 0 000~110 on on off on 111 off sleep mode off 0 0 xxx off off off on/off ( ? ) "x ": dont ? a ? e note: 1.the f h clock will be switched on or of f by confguring the corresponding oscillator enable bit in the slow mode. 2. the f lirc clock can be switched on or of f which is controlled by the wdt function being enabled or disabled in the sleep mode. normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillators. this mode operates allo wing the microco ntroller to operate normally with a clock source will come from hirc oscillators. although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock source. the clock source used will be from f sub . the f sub clock is derived from either the lirc oscillator. sleep mode the sleep mode is entered when an hal t instruction is executed and when the fhiden and fsiden bit are low . in the sleep mode the cpu will be stopped, and the f sub clock to peripheral will be stopped too, but the w atchdog t imer function is decided by user application. idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the fhiden bit in the scc register is low and the fsiden bit in the scc register is high. in the idle0 mode the system oscillator wi ll be i nhibited from dri ving t he cpu but i f t he syst em osc illator i s l ow spee d syst em oscillator, it may continue to provide a clock source to keep some peripheral functions operational. idle1 mode the idle1 mode is entered when an hal t instruction is executed and when the fhiden bit in the scc register is high and the fsiden bit in the scc register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator.
rev. 1.10 40 de?e??e? 1?? ?01? rev. 1.10 41 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu idle2 mode the idle2 mode is entered when an hal t instruction is executed and when the fhiden bit in the scc register is high and the fsiden bit in the scc register is low . in the idle2 mode the system oscillator will be inhibited from driving the cpu but if the system oscillator is high speed system oscillator, it may continue to provide a clock source to keep some peripheral functions operational. control register the re gisters, scc a nd hircc, a re use d t o c ontrol t he syst em c lock a nd t he c orresponding oscillator confgurations. register name bit 7 6 5 4 3 2 1 0 scc cks ? cks1 cks0 fhiden fsiden hircc hircf hircen system operating mode control registers list scc register bit 7 6 5 4 3 2 1 0 na ? e cks ? cks1 cks0 fhiden fsiden r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 cks2~cks0 : system clock selection 000: f 001: f /2 010: f /4 011: f /8 100: f /16 101: f /32 110: f /64 111: f these three bits are used to select which clock is used as the system clock source. in addition to the system clock source directly derived from f or f , a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4~2 unimplemented, read as "0" bit 1 fhiden : high frequency oscillator control when cpu is switched off 0: disable 1: enable this bit is used to control whether the high speed oscillator is activated or stopped when the cpu is switched off by executing an "halt" instruction. bit 0 fsiden : low frequency oscillator control when cpu is switched off 0: disable 1: enable this bi t i s use d t o cont rol whe ther t he l ow spe ed osc illator i s ac tivated or st opped when the cpu is sw itched of f by executing an " halt" instruction. the lirc oscillator i s c ontrolled by t his bi t t ogether wi th t he w dt func tion e nable c ontrol when the wdt function is enabled. if this bit is cleared to 0 but the wdt function is enabled, the lirc oscillator will also be enabled.
rev. 1.10 4 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 4? de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu hircc register bit 7 6 5 4 3 2 1 0 na ? e hircf hircen r/w r r/w por 0 1 bit 7~2 unimplemented, read as "0". bit 1 hircf : hirc oscillator stable fag 0: hirc unstable 1: hirc stable this bit is used to indi cate whe ther the hirc oscilla tor is stable or not. when the hircen bit is s et to 1 to enable the h irc os cillator, the h ircf bit w ill firs t be cleared to 0 and then set to 1 after the hirc oscillator is stable. bit 0 hircen : hirc oscillator enable control 0: disable 1: enable operating mode switching the devi ce c an swi tch bet ween opera ting m odes dynam ically a llowing t he use r t o se lect t he best performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the cks2~cks0 bits in the scc register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the hal t instructio n. when a hal t instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the fhiden and fsiden bit in the scc register. normal f sys =f h ~f h /?4 f h on cpu ?un f sys on f sub on slow f sys =f sub f sub on cpu ?un f sys on f h on/off idle0 halt inst?u?tion exe?uted cpu stop fhiden=0 fsiden=1 f h off f sub on idle1 halt inst?u?tion exe?uted cpu stop fhiden=1 fsiden=1 f h on f sub on idle2 halt inst?u?tion exe?uted cpu stop fhiden=1 fsiden=0 f h on f sub off sleep halt inst?u?tion exe?uted cpu stop fhiden=0 fsiden=0 f h off f sub off
rev. 1.10 4? de?e??e? 1?? ?01? rev. 1.10 4 ? de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes m ore powe r, t he syste m c lock c an swit ch t o run i n t he sl ow mode by se t t he cks2~cks0 bits to "1 11"in the scc register . this will then use the low speed system oscillator which wi ll c onsume l ess po wer. use rs m ay de cide t o do t his fo r c ertain op erations whi ch do no t require high performance and can subsequently reduce power consumption. the slow mode requires this oscillator to be stable before full mode switching occurs. normal mode slow mode cks?~cks0 = 111 sleep mode fhiden=0? fsiden=0 halt inst?u?tion is exe?uted idle0 mode fhiden=0? fsiden=1 halt inst?u?tion is exe?uted idle1 mode fhiden=1? fsiden=1 halt inst?u?tion is exe?uted idle2 mode fhiden=1? fsiden=0 halt inst?u?tion is exe?uted
rev. 1.10 44 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 45 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu slow mode to normal mode switching in slow mode the system clock is derived from f sub . when system clock is switched back to the normal mode from f sub , the cks2~cks0 bits should be set to "000" ~"1 10" and then the system clock will respectively be switched to f h ~ f h /64. however, i f f h i s not use d i n sl ow m ode a nd t hus swi tched of f, i t wi ll t ake som e t ime t o re - oscillate and stabilise when switching to the normal mode from the slow mode. this is monitored using the hircf bit in the hircc register . the time duration required for the high speed system oscillator stabilization is specifed in the a.c. characteristics. normal mode slow mode cks?~cks0 = 000~110 sleep mode fhiden=0? fsiden=0 halt inst?u?tion is exe?uted idle0 mode fhiden=0? fsiden=1 halt inst?u?tion is exe?uted idle1 mode fhiden=1? fsiden=1 halt inst?u?tion is exe?uted idle2 mode fhiden=1? fsiden=0 halt inst?u?tion is exe?uted entering the sleep mode there is only one way for the device to enter the sleep mode and that is to execute the "hal t" instruction in the application program with the fh iden and fsiden bit in scc regis ter equal to "0". when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag t o will be cleared. ? the wdt will be cleared and resume counting as the wdt is enabled. if the wdt is disabled then wdt will be cleared and stopped.
rev. 1.10 44 de?e??e? 1?? ?01? rev. 1.10 45 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the "hal t" instruction in the application program with the fhiden bit in scc register equal to "0" and the fsiden bit in scc register equal to "1". when this instruction is executed under the conditions described above, the following will occur: ? the f h clock will be off and the f sub clock will be on and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag t o will be cleared. ? the wdt will be cleared and resume counting as the wdt is enabled. if the wdt is disabled then wdt will be cleared and stopped entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the "hal t" instruction in the application program wit h the fhiden bit in scc register equal to "1" and the fsiden bit in scc register equal to "1". when this instruction is executed under the conditions described above, the following will occur: ? the f h and f sub clocks will be on and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag t o will be cleared. ? the wdt will be cleared and resume counting as the wdt is enabled. if the wdt is disabled then wdt will be cleared and stopped. entering the idle2 mode there is only one way for the device to enter the idle2 mode and that is to execute the "hal t" instruction in the application program wit h the fhiden bit in scc register equal to "1" and the fsiden bit in scc register equal to "0". when this instruction is executed under the conditions described above, the following will occur: ? the f h clock will be on and the f sub clock will be off and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag t o will be cleared . ? the wdt will be cleared and resume counting as the wdt is enabled. if the wdt is disabled then wdt will be cleared and stopped.
rev. 1.10 4 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 47 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 and idle2 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to t he i/ o pi ns on t he de vice. al l hi gh-impedance i nput pi ns m ust be c onnected t o e ither a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumpti on. this also applies to devices which have dif ferent package types, as there may be unbonbed pins. these must eit her be set up as out puts or if setup as inputs must have pul l-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the lirc oscillator has enabled. in the idle1 and idle 2 mode the high speed oscillator is on, if the peripheral function clock source is derived from the high speed oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps. wake-up to minimise power consumption the device can enter the sleep or idle0~2 mode, where the system clock source to the cpu will be stopped. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow when the device executes the "hal t" instruction, the pdf fag will be set to 1. the pdf fag will be cleare d to 0 if the device experi ences a system power -up or executes the clear w atchdog t imer instruction. if the system is woken up by a wdt overfow , a w atchdog t imer reset will be initiated and the t o fag will be set to 1. the t o fag is set if a wdt time-out occurs and causes a wake-up that only resets the program counter and stack pointer, other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake up the system . when a port a pin wake-up occurs, the program wil l resume executi on at the instruction following the "hal t" instruction. if the system is woken up by an interrupt, then two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "hal t" instruction. in this situation, the interrupt which woke up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag i s se t hi gh be fore e ntering t he sle ep or idl e mode, t he wa ke-up func tion of t he re lated interrupt will be disabled.
rev. 1.10 4? de?e??e? 1?? ?01? rev. 1.10 47 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer c lock sourc e i s prov ided by t he i nternal f lirc c lock wh ich i s suppl ied by t he lirc oscillator . the w atchdog t imer source clock is then subdivided by a ratio of 2 8 to 2 15 to give longer t imeouts, t he a ctual va lue be ing c hosen usi ng t he w s2~ws0 bi ts i n t he w dtc re gister. the l irc i nternal o scillator h as a n a pproximate f requency o f 3 2khz a t a su pply v oltage o f 5 v. however, it should be noted that this specifed internal clock period can vary with v dd , temperature and process variations. the wdt can be enabled/disabled using the wdtc register. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable/disable and reset mcu operation. the wrf software reset fag will be indicated in the rstfc register . these registers control the overall operation of the w atchdog t imer. wdtc register bit 7 6 5 4 3 2 1 0 na ? e we4 we ? we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~ 3 : wdt function software control 10101: disable 01010: enable other values: reset mcu when these bits are changed by the environmental noise or software setting to reset the microcontrolle r, the reset operation will be activated after 2~3 lirc clock cycles and the wrf bit in the rstfc register will be set to 1. bit 2~ 0 : wdt t ime-out period selection 000: 2 8 / f lirc 001: 2 9 /f lirc 010: 2 10 /f lirc 011: 2 11 /f lirc (default) 100: 2 12 /f lirc 101: 2 13 /f lirc 110: 2 14 /f lirc 111: 2 15 /f lirc these three bi ts de termine the di vision rat io of the w atchdog t imer sourece clock, which in turn determines the timeout period. rstfc register bit 7 6 5 4 3 2 1 0 na ? e lvrf wrf r/w r/w r/w por x 0 "x": unknown bit 7~3 unimplemented, read as "0" bit 2 : lvr function reset fag described elsewhere.
rev. 1.10 48 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 49 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu bit 1 unimplemented, read as "0" bit 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bi t i s se t t o 1 by t he w dt c ontrol re gister soft ware re set a nd c leared by t he application pr ogram. not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program. watchdog timer operation the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the w atchdog t imer will overfow and reset the device. w ith regard to the w atchdog t imer enable/disable function, there are fve bits, we4~we0, in the wdtc register to of fer addi tional enable/disable and reset cont rol of the w atchdog t imer. the wdt function will be disabled when the we4~we0 bits are set to a value of 10101b. the wdt function will be enabled if the we4~we0 bits value is equal to 01010b. if the we4~we0 bits are set to any other values by the environmental noise or software setting, except 01010b and 10101b, it will reset the device after 2~3 lirc clock cycles. after power on these bits will have the value of 01010b. we4 ~ we0 bits wdt function 10101b disa ? le 01010b ena ? le any othe ? value reset mcu watchdog timer enable/disable control under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the w atchdog t imer. the frst is a wdt reset, which means a certain value except 01010b and 10101b written into the we4~we0 bit fled, the second is using the w atchdog t imer software clear instructions and the third is via a halt instruction. there is only one method of using software instruction to clear the w atchdog t imer. that is to use the single "clr wdt" instruction to clear the wdt . the maximum time out period is when the 2 15 division ratio is selected. as an example, with a 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 2 15 division ratio, and a minimum timeout of 8ms for the 2 division ration. clr wdt inst?u?tion 8-stage divide? wdt p?es?ale? we4~we0 ?its wdtc registe? reset mcu f lirc f lirc /? 8 8-to-1 mux clr ws?~ws0 wdt ti?e-out (? 8 /f lirc ~ ? 15 /f lirc ) halt inst?u?tion lirc watchdog timer
rev. 1.10 48 de?e??e? 1?? ?01? rev. 1.10 49 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short delay , will be in a well defined state and ready to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is w hen the w atchdog t imer overflow s and resets the microcontroller . a ll types of reset operations result in different register conditions being setup. another reset exists in the form of a low v oltage reset, l vr, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are several ways in which a microcontroller reset can occur , each of which will be described as follows. power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset also ensures that certain other registers are preset to know n conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. v dd powe?-on reset sst ti?e-out t rstd note: t rstd is power-on delay with typical time=50ms power-on reset timing chart low voltage reset lvr the micr ocontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device and provide an mcu reset should the value fall below a certain predefned level. the l vr function is always enabled during the normal and slow modes with a specifc l vr voltage v lvr . if the s upply voltage of the device drops to w ithin a range of 0.9v ~v lvr s uch as might occur w hen changing the batte ry, the l vr will automatically reset the device internally and the l vrf bit in the rstfc register will also be set to1. for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~ v lvr must exist for greater than the value t lvr specifed in the lvd & lvr electrical characteristics. if the low voltage state does not exceed this value, the l vr will ignore the low supply voltage and will not perform a reset function. the actual v lvr is 2.1v , the l vr will reset the device after 2~3 lirc clock cycles. note that the l vr function will be automatically disabled when the device enters the power down mode. lvr inte?nal reset t rstd + t sst note: t rstd is power-on delay with typical time=50ms low voltage reset timing chart
rev. 1.10 50 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 51 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu ? rstfc register bit 7 6 5 4 3 2 1 0 na ? e lvrf wrf r/w r/w r/w por x 0 "x": unknown bit 7~3 unimplemented, read as "0" bit 2 lvrf : lvr function reset fag 0: not occurred 1: occurred this bit is set to 1 when a specifc low voltage reset condition occurs. note that this bit can only be cleared to 0 by the application program. bit 1 unimplemented, read as "0" bit 0 wrf : wdt control register software reset fag described elsewhere. watchdog time-out reset during normal operation the w atchdog time-out reset during normal operation is the same as an l vr reset except that the watchdog time-out fag t o will be set to "1". wdt ti?e-out inte?nal reset t rstd + t sst note: t rstd is power-on delay with typical time=16.7ms wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to "0" and the t o fag will be set to "1". refer to the a.c. characteristics for t details. wdt ti?e-out inte?nal reset t sst wdt time-out reset during sleep or idle timing chart
rev. 1.10 50 de?e??e? 1?? ?01? rev. 1.10 51 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus regis ter and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table. to pdf reset conditions 0 0 powe ? -on ? eset u u lvr ? eset du ? ing normal o ? slow mode ope ? ation 1 u wdt ti ? e-out ? eset du ? ing normal o ? slow mode ope ? ation 1 1 wdt ti ? e-out ? eset du ? ing idle o ? sleep mode ope ? ation note: "u" stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p ? og ? a ? counte ? reset to ze ? o inte ?? upts all inte ?? upts will ? e disa ? led wdt clea ? afte ? ? eset ? wdt ? egins ? ounting ti ? e ? modules ti ? e ? modules will ? e tu ? ned off input/output po ? ts i/o po ? ts will ? e setup as inputs sta ? k pointe ? sta ? k pointe ? will point to the top of the sta ? k the dif ferent kinds of resets all af fect the internal registers of the microcontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will refect the situation for the larger package type.
rev. 1.10 5 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 5? de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu register reset (power on) wdt time-out (normal operation) wdt time-out (halt)* iar0 xxxx xxxx xxxx xxxx uuuu uuuu mp0 xxxx xxxx xxxx xxxx uuuu uuuu iar1 xxxx xxxx xxxx xxxx uuuu uuuu mp1 xxxx xxxx xxxx xxxx uuuu uuuu bp ---- --0 ---- --0 ---- --0 acc xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu tbhp ---- xxxx ---- uuuu ---- uuuu status --00 xxxx --1u uuuu --11 uuuu lvdc --00 0000 --00 0000 --uu uuuu integ ---- 0000 ---- 0000 ---- uuuu scc 000- --00 000- --00 uuu- --uu hircc ---- --01 ---- --01 ---- --uu rstfc ---- -x-0 ---- -u-u ---- -u-u sadol xxxx ---- xxxx ---- uuuu ---- (adrfs=0) uuuu uuuu (adrfs=1) sadoh xxxx xxxx xxxx xxxx uuuu uuuu (adrfs=0) ---- uuuu (adrfs=1) sadc0 0000 0000 0000 0000 uuuu uuuu sadc1 0000 0000 0000 0000 uuuu uuuu pa 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 uuuu uuuu papu 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 uuuu uuuu pas0 0000 0000 0000 0000 uuuu uuuu pas1 0000 0000 0000 0000 uuuu uuuu wdtc 0101 0011 0101 0011 uuuu uuuu pb 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 uuuu uuuu pbpu 0000 0000 0000 0000 uuuu uuuu pbs0 0000 0000 0000 0000 uuuu uuuu pbs1 0000 0000 0000 0000 uuuu uuuu pc ---- 1111 ---- 1111 ---- uuuu pcc ---- 1111 ---- 1111 ----uuuu pcpu ---- 0000 ---- 0000 ---- uuuu tbc 0011 -111 0011 -111 uuuu uuu pcs0 0000 0000 0000 0000 uuuu uuuu scomc -000 ---- -000 ---- -uuu ---- stmc0 0000 0000 0000 0000 uuuu uuuu stmc1 0000 0000 0000 0000 uuuu uuuu stmdl 0000 0000 0000 0000 uuuu uuuu stmdh ---- --00 ---- --00 ---- --uu
rev. 1.10 5? de?e??e? 1?? ?01? rev. 1.10 5 ? de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu register reset (power on) wdt time-out (normal operation) wdt time-out (halt)* stmal 0000 0000 0000 0000 uuuu uuuu stmah ---- --00 ---- --00 ---- --uu chrgen 0000 0000 0000 0000 uuuu uuuu dacc 1--- ---- 1--- ---- u--- ---- sensw --01 0101 --01 0101 --uu uuuu a0vos 0001 0000 0001 0000 uuuu uuuu pgdr ---- ---0 ---- ---0 ---- ---u mfi0 --00 --00 --00 --00 --uu --uu mfi1 --00 --00 --00 --00 --uu --uu mfi ? --00 --00 --00 --00 --uu --uu ptm0c0 0000 0--- 0000 0--- uuuu u--- ptm0c1 0000 0000 0000 0000 uuuu uuuu ptm0dl 0000 0000 0000 0000 uuuu uuuu ptm0dh ---- --00 ---- --00 ---- --uu ptm0al 0000 0000 0000 0000 uuuu uuuu ptm0ah ---- --00 ---- --00 ---- --uu ptm0rpl 0000 0000 0000 0000 uuuu uuuu ptm0rph ---- --00 ---- --00 ---- --uu eea --00 0000 --00 0000 --uu uuuu eed 0000 0000 0000 0000 uuuu uuuu ptm1c0 0000 0--- 0000 0--- uuuu u--- ptm1c1 0000 0000 0000 0000 uuuu uuuu ptm1dl 0000 0000 0000 0000 uuuu uuuu ptm1dh ---- --00 ---- --00 ---- --uu ptm1al 0000 0000 0000 0000 uuuu uuuu ptm1ah ---- --00 ---- --00 ---- --uu ptm1rpl 0000 0000 0000 0000 uuuu uuuu ptm1rph ---- --00 ---- --00 ---- --uu sledc0 0000 0000 0000 0000 uuuu uuuu sledc1 ---- --00 ---- --00 ---- --uu aduda0 0000 0000 0000 0000 uuuu uuuu aduda1 0000 0000 0000 0000 uuuu uuuu aduc0 0-00 0000 0-00 0000 u-uu uuuu aduc1 ---- --00 ---- --00 ---- --uu dacl 0000 0000 0000 0000 uuuu uuuu dach ---- 1000 ---- 1000 ---- uuuu intc0 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 uuuu uuuu intc ? 0000 0000 0000 0000 uuuu uuuu eec ---- 0000 ---- 0000 ---- uuuu note: "-" not implement "u" stands for "unchanged" "x" stands for "unknown"
rev. 1.10 54 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 55 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names p a~pc. these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction "mov a, [m]", where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. register name bit 7 6 5 4 3 2 1 0 pa pa7 pa ? pa5 pa4 pa ? pa ? pa1 pa0 pac pac7 pac ? pac5 pac4 pac ? pac ? pac1 pac0 papu papu7 papu ? papu5 papu4 papu ? papu ? papu1 papu0 pawu pawu7 pawu ? pawu5 pawu4 pawu ? pawu ? pawu1 pawu0 pb pb7 pb ? pb5 pb4 pb ? pb ? pb1 pb0 pbc pbc7 pbc ? pbc5 pbc4 pbc ? pbc ? pbc1 pbc0 pbpu pbpu7 pbpu ? pbpu5 pbpu4 pbpu ? pbpu ? pbpu1 pbpu0 pc pc ? pc ? pc1 pc0 pcc pcc ? pcc ? pcc1 pcc0 pcpu pcpu ? pcpu ? pcpu1 pcpu0 pas0 pas07 pas0 ? pas05 pas04 pas0 ? pas0 ? pas01 pas00 pas1 pas17 pas1 ? pas15 pas14 pas1 ? pas1 ? pas11 pas10 pbs0 pbs07 pbs0 ? pbs05 pbs04 pbs0 ? pbs0 ? pbs01 pbs00 pbs1 pbs17 pbs1 ? pbs15 pbs14 pbs1 ? pbs1 ? pbs11 pbs10 pcs0 pcs07 pcs0 ? pcs05 pcs04 pcs0 ? pcs0 ? pcs01 pcs00 "": uni ? ple ? ented ? ? ead as "0". i/o logic function register list pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high resistors are selected using the relevant pull-high control registers p apu~pcpu, and are implemented using weak pmos transistors. note that the pull-high resistor can be controlled by the relevant pull-high control registers only when the pin-shared functional pin is selected as an input or nmos output. otherwise, the pull-high resistors can not be enabled. pxpu register bit 7 6 5 4 3 2 1 0 na ? e pxpu7 pxpu ? pxpu5 pxpu4 pxpu ? pxpu ? pxpu1 pxpu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pxpun : i/o port x pin pull-high function control 0: disable 1: enable the pxpun bit is used to control the pin pull-high function. here the "x" can be a, b and c. however, the actual available bits for each i/o port may be different.
rev. 1.10 54 de?e??e? 1?? ?01? rev. 1.10 55 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the p awu register . note that the wake-up function can be controlled by the wake-up control registers only when the pin-shared functional pin is selected as general purpose input/output and the mcu enters the power down mode. pawu register bit 7 6 5 4 3 2 1 0 na ? e pawu7 pawu ? pawu5 pawu4 pawu ? pawu ? pawu1 pawu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pawun : port a pin wake-up function control 0: disable 1: enable i/o port control registers each i/o port has its own control register known as p ac~pcc, to control the input/output configuration. w ith t hese c ontrol re gisters, e ach cmos out put or i nput c an be re configured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a "1". this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a "0", the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however , it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pxc register bit 7 6 5 4 3 2 1 0 na ? e pxc7 pxc ? pxc5 pxc4 pxc ? pxc ? pxc1 pxc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pxcn : i/o port x pin type selection 0: output 1: input the pxcn bit is used to control the pin t ype selection. here the "x" can be a, b, and c. however, the actual available bits for each i/o port may be different.
rev. 1.10 5 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 57 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu i/o port source current control the device supports dif ferent source current driving capability for each i/o port. w ith the corresponding selection registers, sledc0 and sledc1, each i/o port can support four levels of the source current driving capability . users should refer to the d.c. characteristics section to select the desired source current for different applications. register name bit 7 6 5 4 3 2 1 0 sledc0 sledc07 sledc0 ? sledc05 sledc04 sledc0 ? sledc0 ? sledc01 sledc00 sledc1 sledc11 sledc10 i/o port source current control registers list sledc0 register bit 7 6 5 4 3 2 1 0 na ? e sledc07 sledc0 ? sledc05 sledc04 sledc0 ? sledc0 ? sledc01 sledc00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 sledc07~sledc06 : pb7~pb4 source current selection 00: source current=level 0 (min.) 01: source current=level 1 10: source current=level 2 11: source current=level 3 (max.) bit 5~4 sledc05~sledc04 : pb3~pb0 source current selection 00: source current=level 0 (min.) 01: source current=level 1 10: source current=level 2 11: source current=level 3 (max.) bit 3~2 sledc03~sledc02 : pa7~pa4 source current selection 00: source current=level 0 (min.) 01: source current=level 1 10: source current=level 2 11: source current=level 3 (max.) bit 1~0 sledc01~sledc00 : pa3~pa0 source current selection 00: source current=level 0 (min.) 01: source current=level 1 10: source current=level 2 11: source current=level 3 (max.) sledc1 register bit 7 6 5 4 3 2 1 0 na ? e sledc11 sledc10 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 sledc11~sledc10 : pc3~pc0 source current selection 00: source current=level 0 (min.) 01: source current=level 1 10: source current=level 2 11: source current=level 3 (max.)
rev. 1.10 5? de?e??e? 1?? ?01? rev. 1.10 57 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu pin-shared functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions , many of these diffculties can be overcome. for these pins, the desired function of the multi-functio n i/o pins is selected by a series of registers via the application program control. pin-shared function selection registers the limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several dif ferent functions and providing a means of function selection, a wide range of dif ferent functions can be incorporated into even relatively small package sizes. the device includes port "x" output function selection register "n", labeled as pxsn, which can select the desired functions of the multi-function pin-shared pins. when t he pi n-shared i nput funct ion i s se lected t o be use d, t he c orresponding i nput a nd out put functions selection should be properly managed. however , if the external interrupt function is selected to be used, the relevant output pin-shared function should be selected as an i/o function and the interrupt input signal should be selected. the m ost i mportant p oint t o n ote i s t o m ake su re t hat t he d esired p in-shared f unction i s p roperly selected and also deselected. t o select the desired pin-shared function, the pin-shared function should frst be correctly selected using the corresponding pin-shared control register . after that the corresponding peripheral functional setting should be confgured and then the peripheral function can be enabled. t o correctly deselect the pin-shared function, the peripheral function should frst be disabled and then the corresponding pin-shared function control register can be modifed to select other pin-shared functions. register name bit 7 6 5 4 3 2 1 0 pas0 pas07 pas0 ? pas05 pas04 pas0 ? pas0 ? pas01 pas00 pas1 pas17 pas1 ? pas15 pas14 pas1 ? pas1 ? pas11 pas10 pbs0 pbs07 pbs0 ? pbs05 pbs04 pbs0 ? pbs0 ? pbs01 pbs00 pbs1 pbs17 pbs1 ? pbs15 pbs14 pbs1 ? pbs1 ? pbs11 pbs10 pcs0 pcs07 pcs0 ? pcs05 pcs04 pcs0 ? pcs0 ? pcs01 pcs00 pin-shared function selection registers list pas0 register bit 7 6 5 4 3 2 1 0 na ? e pas07 pas0 ? pas05 pas04 pas0 ? pas0 ? pas01 pas00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pas07~pas06 : pa3 pin-shared function selection 00: pa3 01: pa3 10: d- 11: an2 bit 5~4 pas05~pas04 : pa2 pin-shared function selection 00: pa2 01: pa2 10: pa2 11: an1
rev. 1.10 58 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 59 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu bit 3~2 pas03~pas02 : pa1 pin-shared function selection 00: pa1 01: pa1 10: d+ 11: an0 bit 1~0 pas01~pas00 : pa0 pin-shared function selection 00: pa0 01: pa0 10: vref for usb auto detector dac input reference voltage 11: vref for adc and usb auto detector dac input reference voltage pas1 register bit 7 6 5 4 3 2 1 0 na ? e pas17 pas1 ? pas15 pas14 pas1 ? pas1 ? pas11 pas10 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pas17~pas16 : pa7 pin-shared function selection 00: pa7 01: pa7 10: a1p 11: an6 bit 5~4 pas15~pas14 : pa6 pin-shared function selection 00: pa6/int0/stpi 01: pa6/int0/stpi 10: pa6/int0/stpi 11: an5 bit 3~2 pas13~pas12 : pa5 pin-shared function selection 00: pa5/stck 01: pa5/stck 10: pa5/stck 11: an4 bit 1~0 pas11~pas10 : pa4 pin-shared function selection 00: pa4 01: stp 10: pa4 11: an3 pbs0 register bit 7 6 5 4 3 2 1 0 na ? e pbs07 pbs0 ? pbs05 pbs04 pbs0 ? pbs0 ? pbs01 pbs00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pbs07~pbs06 : pb3 pin-shared function selection 00: pb3 01: ptp0b 10: pb3 11: pb3 bit 5~4 pbs05~pbs04 : pb2 pin-shared function selection 00: pb2 01: ptp0 10: pb2 11: pb2
rev. 1.10 58 de?e??e? 1?? ?01? rev. 1.10 59 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu bit 3~2 pbs03~pbs02 : pb1 pin-shared function selection 00: pb1/ptpi 01: pb1/ptpi 10: pb1/ptpi 11: pb1/ptpi bit 1~0 pbs01~pbs00 : pb0 pin-shared function selection 00: pb0/ptck/int1 01: pb0/ptck/int1 10: pb0/ptck/int1 11: pb0/ptck/int1 pbs1 register bit 7 6 5 4 3 2 1 0 na ? e pbs17 pbs1 ? pbs15 pbs14 pbs1 ? pbs1 ? pbs11 pbs10 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pbs17~pbs16 : pb7 pin-shared function selection 00: pb7 01: scom3 10: pb7 11: pb7 bit 5~4 pbs15~pbs14 : pb6 pin-shared function selection 00: pb6 01: scom2 10: pb6 11: pb6 bit 3~2 pbs13~pbs12 : pb5 pin-shared function selection 00: pb5 01: scom1 10: pb5 11: pb5 bit 1~0 pbs11~pbs10 : pb4 pin-shared function selection 00: pb4 01: scom0 10: ptp1 11: pb4 pcs0 register bit 7 6 5 4 3 2 1 0 na ? e pcs07 pcs0 ? pcs05 pcs04 pcs0 ? pcs0 ? pcs01 pcs00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pcs07~pcs06 : pc3 pin-shared function selection 00: pc3/ptck1 01: pc3/ptck1 10: pc3/ptck1 11: pc3/ptck1 bit 5~4 pcs05~pcs04 : pc2 pin-shared function selection 00: pc2 01: ptp1b 10: pc2 11: pc2
rev. 1.10 ? 0 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?1 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu bit 3~2 pcs03~pcs02 : pc1 pin-shared function selection 00: pc1/ptp1i 01: pc1/ptp1i 10: pc1/ptp1i 11: pc1/ptp1i bit 1~0 pcs01~pcs00 : pc0 pin-shared function selection 00: pc0 01: pc0 10: pc0 11: pc0 i/o pin structures the acco mpanying diagram illustra tes the internal structure of the i/o logic function. as the exact logical cons truction of the i/o pin will dif fer from this diagram, it is supplied as a guide only to assist with the functional understanding of the logc function i/o pins. the wide range of pin-shared structures does not permit all types to be shown. m u x vdd cont?ol bit data bit data bus w?ite cont?ol registe? chip reset read cont?ol registe? read data registe? w?ite data registe? syste? wake-up wake-up sele?t pa only i/o pin weak pull-up pull-high registe? sele?t q d ck q d ck q q s s logic function input/output structure programming considerations within the user program, one of the frst things to consider is port initi alisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. if the port control registers, p ac~pcc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, p a~pc, are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "set [m].i" and "clr [m].i" instructions . n ote that w hen us ing thes e bit control instructions , a read-modify-w rite operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.
rev. 1.10 ?0 de?e??e? 1?? ?01? rev. 1.10 ? 1 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu timer module C tm one of the most fundamental functions in any microcontroller devices is the ability to control and measure time. t o implement time related functions the device includes several t imer modules, generally abbrevia ted to the name tm. the tms are multi-purpose timi ng units and serve to provide operations such as t imer/counter, input capture, compare match output and single pulse output as we ll a s be ing t he fun ctional uni t for t he ge neration of pw m si gnals. e ach of t he t ms ha s t wo interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the dif ferent tm types are described here with more detailed information provided in the individual standard and periodic tm sections. introduction the device contai ns a standard t ype tm and two periodic t ype tms which have a reference name of stm, ptm0 and ptm1. although similar in nature, the dif ferent tm types vary in their feature complexity. the common features to all of the standard and periodic tms will be described in this section and the detailed operation regarding each of the tm types will be described in separate sections. t he m ain fe atures a nd di fferences be tween t he t wo t ypes of t ms a re sum marised i n t he accompanying table. tm function stm ptm ti ? e ? /counte ? input captu ? e co ? pa ? e mat ? h output pwm channels 1 1 single pulse output 1 1 pwm align ? ent edge edge pwm adjust ? ent pe ? iod & duty duty o ? pe ? iod duty o ? pe ? iod tm function summary tm operation the dif ferent types of tm of fer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a free running count-up counter whose value is then compared with the value of pre-programmed internal comparators. w hen t he f ree r unning c ount-up c ounter h as t he sa me v alue a s t he p re-programmed comparator, known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the clock source which drives the main counter in each tm can originate from various sources. the selection of the required clock source is implemented using the xtnck2~xtnck0 bits in the xtmn control registers, where "x" stands for s or p type tm and "n" stands for the specific tm serial number. for ptm, there is a serial number "n" in the relevant pin or control bits since there are two ptm in the device. the clock source can be a ratio of the system clock, f sys , or the internal high clock, f h , the f sub clock source or the external xtckn pin. the xtckn pin clock source is used to allow an external signal to drive the tm as an external clock source for event counting.
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?? de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu tm interrupts the st andard t ype a nd pe riodic t ype t ms e ach h ave t wo i nternal i nterrupts, o ne f or e ach o f t he internal c omparator a or c omparator p , whi ch ge nerate a t m i nterrupt whe n a c ompare m atch condition occurs. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has one or two tm input pins, with the label xtckn and xtpni respectivel y. the xtmn input pin, xtckn, is essentially a clock source for the xtmn and is selected using the xtnck2~xtnck0 bits in the xtmnc0 register. this external tm input pin allows an external clock source to drive the internal tm. the xtckn input pin can be chosen to have either a rising or falling active edge. the stck and ptckn pins are also used as the external trigger input pin in single pulse output mode for the stm and ptmn respectively. the o ther x tmn i nput p in, st pi o r pt pni, i s t he c apture i nput wh ose a ctive e dge c an b e a r ising edge, a falling edge or both rising and falling edges and the active edge transition type is selected using the stio1~stio0 or ptnio1~ptnio0 bits in the stmc1 or ptmnc1 register respectively . there is another capture input, ptckn, for ptmn capture input mode, which can be used as the external trigger input source except the ptpni pin. the stp only has an output pin, stp , while the ptmn have two output pins, ptpn and ptpnb. the xtpnb is the inverted signal of the xtpn output. the tm output pins can be selected using the corresponding pin-shared function selection bits described in the pin-shared function section. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external xtpn or xtpnb output p in i s a lso t he p in wh ere t he t m g enerates t he pw m o utput wa veform. as t he t m o utput pins are pin-shared with other functions, the tm output function must frst be setup using relevant pin-shared function selection register. stm ptm input output input output stck ? stpi stp ptck0 ? ptp0i ptck1 ? ptp1i ptp0 ? ptp0b ptp1 ? ptp1b tm external pins tm input/output pin selection selecting t o ha ve a t m i nput/output or whe ther t o re tain i ts ot her sha red func tion i s i mplemented using t he r elevant p in-shared f unction se lection r egisters, wi th t he c orresponding se lection b its i n each pin-shared function register corresponding to a tm input/output pin. confguring the selection bits correctly will setup the corresponding pin as a tm input/output. the details of the pin-shared function selection are described in the pin-shared function section. stm stck stp stpi ccr ?aptu?e input ccr output stm function pin control block diagram
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu ptmn ptckn ptpn ptpni ccr ?aptu?e input ccr output ptpnb ptm function pin control block diagram programming considerations the tm counter registers and the capture/compare ccra and ccrp registers, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specifc way. the important point to note is that data transfer to and from the 8-bit buf fer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra and ccrp registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specifc way as described above, it is recommended to us e the " mov" instruction to access the ccra and ccrp low byte registers, named xtmnal and ptmnrpl, using the following access procedures. acces sing the ccra or ccrp low byte registers without following these access procedures will result in unpredictable values. data bus 8-?it buffe? xtmndh xtmndl xtmnah xtmnal xtmn counte? registe? (read only) xtmn ccra registe? (read/w?ite) ptmnrph ptmnrpl ptmn ccrp registe? (read/w?ite) the following steps show the read and write procedures: ? writing data to ccra or ccrp ? step 1. w rite data to low byte xtmnal or ptmnrpl C note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte xtmnah or ptmnrph C here data is written directly to the high byte regis ters and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra or ccrp ? step 1. read data from the high byte xtmndh, xtmnah or ptmnrph C here d ata i s r ead d irectly f rom t he hi gh b yte r egisters a nd si multaneously d ata i s l atched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte xtmndl, xtmnal or ptmnrpl C this step reads data from the 8-bit buffer.
rev. 1.10 ? 4 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?5 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu standard type tm C stm the standard t ype tm contains fve operating modes, which are compare match output, t imer/ event counter , capture input, single pulse output and pwm output modes. the standard tm can be controlled with two external input pins and can drive one external output pin. f sys f sys /4 f h /?4 f h /1? f sub stck 000 001 010 011 100 101 110 111 stck?~stck0 10-?it count-up counte? ?-?it co?pa?ato? p ccrp ?7~?9 ?0~?9 10-?it co?pa?ato? a ston stpau co?pa?ato? a mat?h co?pa?ato? p mat?h counte? clea? 0 1 output cont?ol pola?ity cont?ol stp stoc stm1? stm0 stio1? stio0 stmaf inte??upt stmpf inte??upt stpol ccra stcclr edge dete?to? stpi stio1? stio0 pin-sha?ed cont?ol pas1 f sub standard type tm block diagram standard tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal clock source. there are also tw o internal comparators w ith the names , comparator a and comparator p . these comparators will compare the value in the counter with ccrp and ccra registers. t he ccrp is 3-bit wide whose value is compared with the highest 3 bits in the counter while the ccra is the 10 bits and therefore compares with all counter bits. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear t he c ounter b y c hanging t he st on b it f rom l ow t o h igh. t he c ounter wi ll a lso b e c leared automatically by a counter overfow or a compare match with one of its associated comparators. when thes e conditions occur , a tm interrupt s ignal w ill als o us ually be generated. the s tandard type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources and can also control an output pin. all operating setup conditions are selected using relevant internal registers. standard type tm register description overall operation of the standard tm is controlled using series of registers. a read only register pair e xists t o st ore t he i nternal c ounter 10 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as three ccrp bits. register name bit 7 6 5 4 3 2 1 0 stmc0 stpau stck ? stck1 stck0 ston strp ? strp1 strp0 stmc1 stm1 stm0 stio1 stio0 stoc stpol stdpx stcclr stmdl d7 d ? d5 d4 d ? d ? d1 d0 stmdh d9 d8 stmal d7 d ? d5 d4 d ? d ? d1 d0 stmah d9 d8 10-bit standard tm register list
rev. 1.10 ?4 de?e??e? 1?? ?01? rev. 1.10 ? 5 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu stmc0 register bit 7 6 5 4 3 2 1 0 na ? e stpau stck ? stck1 stck0 ston strp ? strp1 strp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 stpau : stm counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal c ounter ope ration. w hen i n a pa use c ondition t he st m wi ll rem ain powe red up a nd c ontinue t o c onsume po wer. t he c ounter wi ll re tain i ts re sidual va lue whe n this bit changes from low to high and res ume counting from this value w hen the bit changes to a low value again. bit 6~4 stck2~stck0 : select stm counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f 101: f 110: stck rising edge clock 111: stck falling edge clock these three bits are used to select the clock source for the stm. the external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f is the system clock, while f and f tbc are other internal clocks, the detai ls of which can be found in the oscillator section. bit 3 ston : stm counter on/off control 0: off 1: on this bit controls the overall on/of f function of the stm. setting the bit high enables the counter to run, clearing the bit disables the stm. clearing this bit to zero will stop the counter from counting and turn of f the stm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the stm is in the c ompare ma tch out put mod e or t he pw m ou tput mod e or si ngle pul se out put mode then the stm output pin will be reset to its initial condition, as specifed by the stoc bit, when the ston bit changes from low to high. bit 2~0 strp2~strp0 : stm ccrp 3-bit register, compared with the stm counter bit 9~bit 7 comparator p match period 000: 1024 stm clocks 001: 128 stm clocks 010: 256 stm clocks 011: 384 stm clocks 100: 512 stm clocks 101: 640 stm clocks 110: 768 stm clocks 111: 896 stm clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared w ith the internal counter s highes t three bits. the result of this comparison can be selected to clear the internal counter if the stcclr bit is set to zero. setting the stcclr bit to zero ensures that a compare match with the ccrp values will re set t he i nternal c ounter. as t he ccrp bi ts a re onl y c ompared wi th t he hi ghest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overfow at its maximum value.
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?7 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu stmc1 register bit 7 6 5 4 3 2 1 0 na ? e stm1 stm0 stio1 stio0 stoc stpol stdpx stcclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 stm1~stm0 : select stm operating mode 00: compare match output mode 01: capture input mode 10: pwm output mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the stm. t o ensure reliable operation the stm should be switched of f before any changes are made to the stm1 and stm0 bits. in the t imer/counter mode, the stm output pin state is undefned. bit 5~4 stio1~stio0 : select stm function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm output mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of stpi 01: input capture at falling edge of stpi 10: input capture at falling/rising edge of stpi 11: input capture disabled timer/counter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match o utput mode, the stio1~s tio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the stio1~stio0 bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the st oc bit. note that the output level requested by the stio1~stio0 bits must be dif ferent from the initial value setup using the st oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state, it can be res et to its initial level by changing the level of the ston bit from low to high. in the pwm mode, the stio1 and stio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odifed by c hanging t hese t wo bi ts. it i s ne cessary t o c hange t he va lues of the stio1 and stio0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the stio1 and stio0 bits are changed when the tm is running.
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 7 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu bit 3 stoc : stp output control bit compare match output mode 0: initial low 1: initial high pwm output mode/single pulse output mode 0: active low 1: active high this is the output control bit for the stm output pin. its operation depends upon whether stm is being used in the compare match output mode or in the pwm output mode/ single puls e output mode. it has no ef fect if the stm is in the t imer/counter mode. in t he com pare ma tch out put mode i t de termines t he l ogic l evel of t he st m output pin before a compare match occurs. in the pwm output mode it determines if the pwm signal is active high or active low . in the single pulse output mode it determines the logic level of the stm output pin when the ston bit changes from low to high. bit 2 stpol : stp output polarity control 0: non-invert 1: invert this bit controls the polarity of the stm output pin. when the bit is set high the stm output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the stm is in the t imer/counter mode. bit 1 stdpx : stm pwm period/duty control 0: ccrp C period; ccra - duty 1: ccrp C duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 stcclr : select stm counter clear condition 0: stm comparator p match 1: stm comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he standard stm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the stcclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the stcclr bit is not used in the pwm output mode, single pulse or input capture mode. stmdl register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : stm counter low byte register bit 7 ~ bit 0 stm 10-bit counter bit 7 ~ bit 0 stmdh register bit 7 6 5 4 3 2 1 0 na ? e d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 d9~d8 : stm counter high byte register bit 1 ~ bit 0 stm 10-bit counter bit 9 ~ bit 8
rev. 1.10 ? 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?9 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu stmal register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : stm ccra low byte register bit 7 ~ bit 0 stm 10-bit counter bit 7 ~ bit 0 stmah register bit 7 6 5 4 3 2 1 0 na ? e d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 d9~d8 : stm ccra high byte register bit 1 ~ bit 0 stm 10-bit counter bit 9 ~ bit 8 standard type tm operating modes the standard t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the stm1 and stm0 bits in the stmc1 register. compare output mode to select this mode, bits stm1 and stm0 in the stmc1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the stcclr bit is low , there are two ways in which the counter can be cleared. one is when a compare match from comparator p , the other is when the ccrp bits are all zero which allows the counter t o ov erfow. he re bo th st maf a nd st mpf i nterrupt re quest fa gs fo r co mparator a a nd comparator p respectively, will both be generated. if the stcclr bit in the stmc1 register is high then the counter will be cleared when a compare match oc curs from com parator a. howe ver, he re onl y t he st maf i nterrupt re quest fa g wi ll be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when stcclr is high no stmpf interru pt request fag will be generated. in the compare match output mode, the ccra cannot be set to "0". if the ccra bits are all zero, the counter will overfow when it reaches its maximum 10-bit, 3ff hex, value, however here the stmaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the stm output pin, will change state. the stm output pin condition however only changes state when an stmaf interrupt request fag is generated after a compare match occurs from comparator a . the s tmpf interrupt reques t fag, g enerated f rom a c ompare m atch o ccurs f rom c omparator p , wi ll h ave n o e ffect o n t he st m output pin. the way in which the stm output pin changes state are determined by the condition of the stio1 and stio0 bits in the stmc1 register . the stm output pin can be selected using the stio1 and stio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the stm output pin, which is setup after the st on bit changes from low to high, is setup using the st oc bit. note that if the stio1 and stio0 bits are zero then no pin change will take place.
rev. 1.10 ?8 de?e??e? 1?? ?01? rev. 1.10 ? 9 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu counte? value 0x?ff ccrp ccra ston stpau stpol ccrp int. flag stmpf ccra int. flag stmaf stm o/p pin ti?e ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed ?y ccrp value pause resu?e stop counte? resta?t stcclr = 0; stm [1:0] = 00 output pin set to initial level low if stoc=0 output toggle with stmaf flag note stio [1:0] = 10 a?tive high output sele?t he?e stio [1:0] = 11 toggle output sele?t output not affe?ted ?y stmaf flag. re?ains high until ?eset ?y ston ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when stpol is high stm compare match output C stcclr=0 note: 1. w ith stcclr=0 a comparator p match will clear the counter 2. the tm output pin controlled only by the stmaf fag 3. the output pin reset to initial state by a ston bit rising edge
rev. 1.10 70 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 71 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu counte? value 0x?ff ccrp ccra ston stpau stpol ccrp int. flag stmpf ccra int. flag stmaf stm o/p pin ti?e ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed ?y ccra value pause resu?e stop counte? resta?t stcclr = 1; stm [1:0] = 00 output pin set to initial level low if stoc=0 output toggle with stmaf flag note stio [1:0] = 10 a?tive high output sele?t he?e stio [1:0] = 11 toggle output sele?t output not affe?ted ?y stmaf flag. re?ains high until ?eset ?y ston ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when stpol is high stmpf not gene?ated no stmaf flag gene?ated on ccra ove?flow output does not ?hange stm compare match output C stcclr=1 note: 1. w ith stcclr=1 a comparator a match will clear the counter 2. the tm output pin controlled only by the stmaf fag 3. the output pin reset to initial state by a ston rising edge 4. the stmpf fag is not generated when stcclr=1
rev. 1.10 70 de?e??e? 1?? ?01? rev. 1.10 71 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu timer/counter mode to select this mode, bits stm1 and stm0 in the stmc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the s ame interrupt flags . the exception is that in the t imer/counter m ode the s tm output pin is not used. therefore the above description and t iming diagrams for the compare match out put mod e c an be use d t o un derstand i ts fu nction. as t he st m ou tput pi n i s no t use d i n this mode, the pin can be used as a normal i/o pin or other pin-shared function by setting pin-share function register. pwm output mode to select this mode, bits stm1 and stm0 in the stmc1 register should be set to 10 respectively and als o the stio 1 and stio 0 bits should be set to 10 res pectively. the pwm function w ithin the stm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the stm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely f lexible. i n t he pw m o utput m ode, t he st cclr b it h as n o e ffect a s t he pwm period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the stdpx bit in the stmc1 register . the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the st oc bit in the stmc1 register is used to select the required polarity of the pwm waveform while the two stio1 and stio0 bits are used to enable the pwm output or to force the stm output pin to a fxed high or low level. the stpol bit is used to reverse the polarity of the pwm output waveform. ? 10-bit stm, pwm output mode, edge-aligned mode, stdpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod 1 ? 8 ? 5 ? ? 84 51 ? ? 40 7 ? 8 89 ? 10 ? 4 duty ccra if f sys =8mhz, tm clock source is f sys /4, ccrp=100b and ccra =128, the stm pwm output frequency=(f sys /4)/512=f sys /2048=3.906khz, duty=128/512=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? 10-bit stm, pwm output mode, edge-aligned mode, stdpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod ccra duty 1 ? 8 ? 5 ? ? 84 51 ? ? 40 7 ? 8 89 ? 10 ? 4 the pwm output period is determined by the ccra register value together with the stm clock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.10 7 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 7? de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu counte? value ccrp ccra ston stpau stpol ccrp int. flag stmpf ccra int. flag stmaf stm o/p pin (stoc=1) ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? stop if ston ?it low counte? reset when ston ?etu?ns high stdpx = 0; stm [1:0] = 10 pwm duty cy?le set ?y ccra pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when stpol = 1 pwm pe?iod set ?y ccrp stm o/p pin (stoc=0) pwm output mode C stdpx=0 note: 1. here stdpx=0 C counter cleared by ccrp 2. a counter clear sets pwm period 3. the internal pwm function continues running even when stio[1:0]=00 or 01 4. the stcclr bit has no infuence on pwm operation.
rev. 1.10 7? de?e??e? 1?? ?01? rev. 1.10 7 ? de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu counte? value ccrp ccra ston stpau stpol ccrp int. flag stmpf ccra int. flag stmaf stm o/p pin (stoc=1) ti?e counte? ?lea?ed ?y ccra pause resu?e counte? stop if ston ?it low counte? reset when ston ?etu?ns high stdpx = 1; stm [1:0] = 10 pwm duty cy?le set ?y ccrp pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when stpol = 1 pwm pe?iod set ?y ccra stm o/p pin (stoc=0) pwm output mode C stdpx=1 note: 1. here stdpx=1 C counter cleared by ccra 2. a counter clear sets pwm period 3. the internal pwm function continues even when stio[1:0]=00 or 01 4. the stcclr bit has no infuence on pwm operation.
rev. 1.10 74 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 75 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu single pulse mode to select this mode, bits stm1 and stm0 in the stmc1 register should be set to 10 respectively and also the stio1 and stio0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the stm output pin. the trigger for the pulse output lead ing edge is a low to high transition of the st on bit, which can be i mplemented using t he a pplication progra m. however i n t he single pulse mode, t he st on bi t can also be made to automatically change from low to high using the external stck pin, which will in turn initiate the single pulse output. when the st on bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the st on bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the ston bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the st on bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a stm interrupt. the counter can only be reset back to zero when the st on bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the stcclr and stdpx bits are not used in this mode. ston ?it 0 1 s/w co??and setston o? stck pin t?ansition ston ?it 1 0 ccra t?ailing edge s/w co??and clrston o? ccra co?pa?e mat?h stp output pin pulse width = ccra value ccra leading edge single pulse generation
rev. 1.10 74 de?e??e? 1?? ?01? rev. 1.10 75 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu counte? value ccrp ccra ston stpau stpol ccrp int. flag stmpf ccra int. flag stmaf stm o/p pin (stoc=1) ti?e counte? stopped ?y ccra pause resu?e counte? stops ?y softwa?e counte? reset when ston ?etu?ns high stm [1:0] = 10 ; stio [1:0] = 11 pulse width set ?y ccra output inve?ts when stpol = 1 no ccrp inte??upts gene?ated stm o/p pin (stoc=0) stck pin softwa?e t?igge? clea?ed ?y ccra ?at?h stck0 pin t?igge? auto. set ?y stck pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse mode note: 1. counter stopped by ccra match 2. ccrp is not used 3. the pulse is triggered by setting the ston bit high 4. in the single pulse mode, stio [1:0] must be set to "11" and cannot be changed
rev. 1.10 7 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 77 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu capture input mode to select this mode bits stm1 and stm0 in the stmc1 register should be set to 01 respectively . this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and can therefore be used for applications such as pulse width measurement. the external signal is supplied on t he st pi, whose a ctive e dge c an be e ither a ri sing e dge, a fa lling e dge or bot h ri sing and falling edges; the active edge transition type is selected using the stio1 and stio0 bits in the stmc1 register . the counter is started when the st on bit changes from low to high which is initiated using the application program. when t he r equired e dge t ransition a ppears o n t he st pi t he p resent v alue i n t he c ounter wi ll b e latched into the ccra registers and a stm interrupt generated. irrespective of what events occur on the stpi the counter will continue to free run until the st on bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a stm interrup t will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the stio1 and stio0 bits can select t he a ctive t rigger e dge on t he st pi t o be a ri sing e dge, fa lling e dge or bot h e dge t ypes. if the stio1 and stio0 bits are both set high, then no capture operation will take place irrespective of what happens on the stpi, however it must be noted that the counter will continue to run. the stcclr and stdpx bits are not used in this mode.
rev. 1.10 7? de?e??e? 1?? ?01? rev. 1.10 77 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu counte? value yy ccrp ston stpau ccrp int. flag stmpf ccra int. flag stmaf ccra value ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? reset stm [1:0] = 01 stm ?aptu?e pin stpi xx counte? stop stio [1:0] value xx yy xx yy a?tive edge a?tive edge a?tive edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disa?le captu?e capture input mode note: 1. stm[1:0]=01 and active edge set by the stio[1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. the stcclr and stdpx bits are not used 4. no output function C stoc and stpol bits are not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.10 78 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 79 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu periodic type tm C ptm the pe riodic t ype t m c ontains fv e o perating m odes, wh ich a re c ompare ma tch ou tput, t imer/ event counter , capture input, single pulse output and pwm output modes. the periodic tm can be controlled with two external input pins and can drive two external output pins. ptckn 10-?it count-up counte? 10-?it co?pa?ato? p ccrp 10-?it co?pa?ato? a output cont?ol pola?ity cont?ol pin cont?ol ptpn ccra edge dete?to? ptpni pin cont?ol ptpnb ptncclr f sys f sys /4 f h /?4 f h /1? f sub ptnck?~ptnck0 ptnon ptnpau co?pa?ato? a mat?h co?pa?ato? p mat?h counte? clea? ptnoc ptnm1? ptnm0 ptnio1? ptnio0 ptmnaf inte??upt ptmnpf inte??upt ptnpol pxsn ptnio1? ptnio0 f sub pxsn ptncapts 000 001 010 011 100 101 110 111 ?0~?9 ?0~?9 0 1 1 0 periodic type tm block diagram (n=0 or 1) periodic tm operation the periodic t ype tm core is a 10-bit count-up counter which is driven by a user selectable internal or e xternal c lock sourc e. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a and comparator p . these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp comparator is 10-bit wide. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the ptnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a ptmn interrupt signal will also usually be generated. the periodic type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control more than one output pin. all operating setup conditions are selected using relevant internal registers. periodic type tm register description overall operation of the periodic t ype tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the int ernal 10-bit ccra val ue and ccrp val ue. the remaining two registers are control registers which setup the different operating and control modes. register name bit 7 6 5 4 3 2 1 0 ptmnc0 ptnpau ptnck ? ptnck1 ptnck0 ptnon ptmnc1 ptnm1 ptnm0 ptnio1 ptnio0 ptnoc ptnpol ptncapts ptncclr ptmndl d7 d ? d5 d4 d ? d ? d1 d0 ptmndh d9 d8 ptmnal d7 d ? d5 d4 d ? d ? d1 d0 ptmnah d9 d8 ptmnrpl d7 d ? d5 d4 d ? d ? d1 d0 ptmnrph d9 d8 10-bit periodic tm register list (n=0 or 1)
rev. 1.10 78 de?e??e? 1?? ?01? rev. 1.10 79 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu ptmnc0 register bit 7 6 5 4 3 2 1 0 na ? e ptnpau ptnck ? ptnck1 ptnck0 ptnon r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 ptnpau : ptmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the ptmn will remain powered up a nd c ontinue t o c onsume po wer. t he c ounter wi ll re tain i ts re sidual va lue whe n this bit changes from low to high and res ume counting from this value w hen the bit changes to a low value again. bit 6~4 ptnck2~ptnck0 : select ptmn counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f 101: f 110: ptckn rising edge clock 111: ptckn falling edge clock these three bits are used to select the clock source for the ptmn. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source is the system clock, while f and f are other internal clocks, the details of which can be found in the oscillator section. bit 3 ptnon : ptmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the ptmn. setting the bit high enables the counter to run, clearing the bit disables the ptmn. clearing this bit to zero will stop the counter from counting and turn of f the ptmn which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the ptmn is in the compare match output mode, pwm output mode or single pulse output mode then the ptmn output pin will be reset to its initial condition, as specifed by the ptnoc bit, when the ptnon bit changes from low to high. bit 2~0 unimplemented, read as "0" ptmnc1 register bit 7 6 5 4 3 2 1 0 na ? e ptnm1 ptnm0 ptnio1 ptnio0 ptnoc ptnpol ptncapts ptncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 ptnm1~ptnm0 : select ptmn operating mode 00: compare match output mode 01: capture input mode 10: pwm output mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the ptmn. t o ensure reliable operation the ptmn should be switched of f before any changes are made to the ptnm1 and ptnm0 bits. in the t imer/counter mode, the ptmn output pin control must be disabled.
rev. 1.10 80 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 81 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu bit 5~4 ptnio1~ptnio0 : select ptmn function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm output mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of ptpni or ptckn 01: input capture at falling edge of ptpni or ptckn 10: input capture at falling/rising edge of ptpni or ptckn 11: input capture disabled timer/counter mode unused these two bits are used to determine how the ptmn output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the ptmn is running. in the compare match output mode, the ptnio1 and ptnio0 bits determine how the ptmn output pin changes state when a compare match occurs from the comparator a. the ptmn output pin can be setup to switch high, switch low or to toggle its present state whe n a c ompare m atch oc curs from t he com parator a. w hen t he bi ts a re bot h zero, then no change will take place on the output. the initial value of the ptmn output pin should be setup using the ptnoc bit in the ptmnc1 register . note that the output level requested by the ptnio1 and ptnio0 bits must be dif ferent from the initial value setup using the ptnoc bit otherwise no change will occur on the ptmn output pin when a compare match occurs. after the ptmn output pin changes state, it can be reset to its initial level by changing the level of the ptnon bit from low to high. in the pwm mode, the pt nio1 and pt nio0 bits dete rmine how the pt mn out put pin changes state when a certain compare match condition occurs. the pwm output function i s m odified b y c hanging t hese t wo b its. i t i s n ecessary t o o nly c hange t he values of t he pt nio1 a nd pt nio0 bi ts onl y a fter t he t m ha s be en swi tched of f. unpredictable pwm outputs will occur if the ptnio1 and ptnio0 bits are changed when the ptmn is running. bit 3 ptnoc : ptpn output control bit compare match output mode 0: initial low 1: initial high pwm output mode/single pulse output mode 0: active low 1: active high this is the output control bit for the ptmn output pin. its operation depends upon whether ptmn is being used in the compare match output mode or in the pwm mode/single pulse output mode. it has no ef fect if the ptmn is in the t imer/counter mode. in the compare match output mode it determines the logic level of the ptmn output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 ptnpol : ptpn output polarity control 0: non-invert 1: invert this bit controls the polarity of the ptpn output pin. when the bit is set high the ptmn output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the ptmn is in the t imer/counter mode.
rev. 1.10 80 de?e??e? 1?? ?01? rev. 1.10 81 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu bit 1 ptncapts : ptmn capture trigger source selection 0: from ptpni pin 1: from ptckn pin bit 0 ptncclr : select ptmn counter clear condition 0: ptmn comparator p match 1: ptmn comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he periodic t m c ontains t wo c omparators, com parator a a nd com parator p , e ither of which can be selected to clear the internal counter . w ith the ptncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the ptncclr bit is not used in the pwm mode, single pulse or capture input mode. ptmndl register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : ptmn counter low byte register bit 7 ~ bit 0 ptmn 10-bit counter bit 7 ~ bit 0 ptmndh register bit 7 6 5 4 3 2 1 0 na ? e d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 d9~d8 : ptmn counter high byte register bit 1 ~ bit 0 ptmn 10-bit counter bit 9 ~ bit 8 ptmnal register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : ptmn ccra low byte register bit 7 ~ bit 0 ptmn 10-bit ccra bit 7 ~ bit 0 ptmnah register bit 7 6 5 4 3 2 1 0 na ? e d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 d9~d8 : ptmn ccra high byte register bit 1 ~ bit 0 ptmn 10-bit ccra bit 9 ~ bit 8
rev. 1.10 8 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 8? de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu ptmnrpl register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : ptmn ccrp low byte register bit 7 ~ bit 0 ptmn 10-bit ccrp bit 7 ~ bit 0 ptmnrph register bit 7 6 5 4 3 2 1 0 na ? e d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 d9~d8 : ptmn ccrp high byte register bit 1 ~ bit 0 ptmn 10-bit ccrp bit 9 ~ bit 8 periodic type tm operating modes the standard t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the ptnm1 and ptnm0 bits in the ptmnc1 register. compare output mode to select this mode, bits ptnm1 and ptnm0 in the ptmnc1 register , should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare match from comparator a and a compare match from comparator p . when the ptncclr bit is low , there are two ways in which the counter can be cleared. one is when a compare match from comparator p , the other is when the ccrp bits are all zero which allows the counter to overfow . here both ptmnaf and ptmnpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the ptncclr bit in the ptmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the ptmnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when ptncclr is high no ptmnpf interrupt request fag will be generated. in the compare match output mode, the ccra can not be cleared to zero. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the ptmnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the ptmn output pin, will change state. the ptmn output pin condition however only changes state when a ptmnaf interrupt request fag is generated after a compare match occurs from comparator a. the ptmnpf interrupt request fag, generated from a compare match occurs from comparator p , will have no ef fect on the ptmn output pin. the way in which the ptmn output pin changes state are determined by the condition of the ptnio1 and ptnio0 bits in the ptmnc1 register . the ptmn output pin can be selected using the pt nio1 a nd pt nio0 bi ts t o go hi gh, t o go l ow or t o t oggle fr om i ts pre sent c ondition whe n a compare match occurs from comparator a. the initial condition of the ptmn output pin, which is setup afte r the ptnon bit changes from low to high, is setup using the ptnoc bit. note that if the ptnio1 and ptnio0 bits are zero then no pin change will take place.
rev. 1.10 8? de?e??e? 1?? ?01? rev. 1.10 8 ? de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu counter value 0x?ff ccrp ccra ptnon ptnpau ptnpol ccrp int. flag ptmnpf ccra int. flag ptmnaf ptmn o/p pin time ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed ?y ccrp value pause resu?e stop counte? resta?t ptncclr = 0; ptnm[1:0] = 00 output pin set to initial level low if ptnoc=0 output toggle with ptmnaf flag note ptnio [1:0] = 10 a?tive high output sele?t he?e ptnio [1:0] = 11 toggle output sele?t output not affe?ted ?y ptmnaf flag. re?ains high until ?eset ?y ptnon ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ptnpol is high compare match output mode C ptncclr=0 (n=0 or 1) note: 1. w ith ptncclr=0 a comparator p match will clear the counter 2. the ptmn output pin is controlled only by the ptmnaf fag 3. the output pin is reset to its initial state by a ptnon bit rising edge
rev. 1.10 84 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 85 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu counter value 0x?ff ccrp ccra ptnon ptnpau ptnpol ccrp int. flag ptmnpf ccra int. flag ptmnaf ptmn o/p pin time ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed ?y ccra value pause resu?e stop counte? resta?t ptncclr = 1; ptnm[1:0] = 00 output pin set to initial level low if ptnoc=0 output toggle with ptmnaf flag note ptnio [1:0] = 10 a?tive high output sele?t he?e ptnio [1:0] = 11 toggle output sele?t output not affe?ted ?y ptmnaf flag. re?ains high until ?eset ?y ptnon ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ptnpol is high ptmnpf not gene?ated no ptmnaf flag gene?ated on ccra ove?flow output does not ?hange compare match output mode C ptncclr=1 (n=0 or 1) note: 1. w ith ptncclr=1 a comparator a match will clear the counter 2. the ptmn output pin is controlled only by the ptmnaf fag 3. the output pin is reset to its initial state by a ptnon bit rising edge 4. a ptmnpf fag is not generated when ptncclr=1
rev. 1.10 84 de?e??e? 1?? ?01? rev. 1.10 85 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu timer/counter mode to se lect t his mode , bi ts pt nm1 and pt nm0 i n t he pt mnc1 regi ster should be se t t o 1 1 respectively. the t imer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits ptnm1 and ptnm0 in the ptmnc1 register should be set to 10 respectively. the pwm function within the ptmn is useful for applica tions which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the ptmn output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extre mely fexible. in the pwm output mode, the ptncclr bit has no ef fect on the pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the ptnoc bit in the ptmnc1 register is used to select the required polari ty of the pwm waveform whi le the two ptnio1 and ptnio0 bi ts are used to enable the pwm output or to force the ptmn output pin to a fxed high or low level. the ptnpol bit is used to reverse the polarity of the pwm output waveform. ? 10-bit ptmn, pwm mode, edge-aligned mode ccrp 1~1023 0 pe ? iod 1~10 ?? 10 ? 4 duty ccra if f sys =8mhz, ptmn clock source select f sys /4, ccrp=512 and ccra=128, the ptmn pwm output frequency=(f sys /4)/512=f sys /2048=3.906khz, duty=128/(2256)=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%.
rev. 1.10 8 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 87 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu counter value ccrp ccra ptnon ptnpau ptnpol ccrp int. flag ptmnpf ccra int. flag ptmnaf ptmn o/p pin (ptnoc=1) time counte? ?lea?ed ?y ccrp pause resu?e counte? stop if ptnon ?it low counte? reset when ptnon ?etu?ns high ptnm[1:0] = 10 pwm duty cy?le set ?y ccra pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ptnpol = 1 pwm pe?iod set ?y ccrp ptmn o/p pin (ptnoc=0) pwm output mode (n=0 or 1) note: 1. counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when ptnio[1:0]=00 or 01 4. the ptncclr bit has no infuence on pwm operation
rev. 1.10 8? de?e??e? 1?? ?01? rev. 1.10 87 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu single pulse mode to select this mode, bits ptnm1 and ptnm0 in the ptmnc1 register should be set to 10 respectively and also the ptnio1 and ptnio0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the ptmn output pin. the t rigger f or t he p ulse o utput l eading e dge i s a l ow t o h igh t ransition o f t he pt non b it, wh ich can be implement ed using the application program. however in the single pulse mode, the ptnon bit can also be made to automatically change from low to high using the external ptckn pin, which will in turn initiate the single pulse output. when the ptnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the ptnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the ptnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compa re match from comparator a will also automatically clear the ptnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a ptmn interrupt. the counter can only be res et back to zero w hen the ptno n bit changes from low to high w hen the counter restarts. in the single pulse mode ccrp is not used. the ptncclr bit is not used in this mode. ptnon ?it 0 1 s/w co??and setptnon o? ptckn pin t?ansition ptnon ?it 1 0 ccra t?ailing edge s/w co??and clrptnon o? ccra co?pa?e mat?h ptpn output pin pulse width = ccra value ccra leading edge single pulse generation (n=0 or 1)
rev. 1.10 88 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 89 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu counter value ccrp ccra ptnon ptnpau ptnpol ccrp int. flag ptmnpf ccra int. flag ptmnaf ptmn o/p pin (ptnoc=1) time counte? stopped ?y ccra pause resu?e counte? stops ?y softwa?e counte? reset when ptnon ?etu?ns high ptnm[1:0] = 10 ; ptnio[1:0] = 11 pulse width set ?y ccra output inve?ts when ptnpol = 1 no ccrp inte??upts gene?ated ptmn o/p pin (ptnoc=0) ptckn pin softwa?e t?igge? clea?ed ?y ccra ?at?h ptckn pin t?igge? auto. set ?y ptckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse mode (n=0 or 1) note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the ptckn pin or by setting the ptnon bit high 4. a ptckn pin active edge will automatically set the ptnon bit high 5. in the single pulse mode, ptnio[1:0] must be set to "11" and cannot be changed.
rev. 1.10 88 de?e??e? 1?? ?01? rev. 1.10 89 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu capture input mode to select this mode bits ptnm1 and ptnm0 in the ptmnc1 register should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal i s sup plied on t he pt pni or pt ckn p in whi ch i s se lected usi ng t he pt ncapts b it i n t he ptmnc1 register . the input pin active edge can be either a rising edge, a falling edge or both rising and fallin g edges; the active edge transition type is selected using the ptnio1 and ptnio0 bits in the ptmnc1 register . the counter is started when the ptnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the ptpni or ptckn pin the present value in the counter will be latched into the ccra registers and a ptmn interrupt generated. irrespective of what events occur on the ptpni or ptckn pin, the counter will continue to free run until the ptnon bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a ptmn interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the ptnio1 and ptnio0 bits can select the active trigger edge on the ptpni or ptckn pin to be a rising edge, falling edge or both edge types. if the ptnio1 and ptnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the ptpni or ptckn pin, however it must be noted that the counter will continue to run. as the ptpni or ptckn pin is pin shared with other functions, care must be taken if the ptmn is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the ptncclr, ptnoc and ptnpol bits are not used in this mode.
rev. 1.10 90 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 91 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu counter value yy ccrp ptnon ptnpau ccrp int. flag ptmnpf ccra int. flag ptmnaf ccra value time counte? ?lea?ed ?y ccrp pause resu?e counte? reset ptnm[1:0] = 01 ptmn captu?e pin ptpni o? ptckn xx counte? stop ptnio [1:0] value a?tive edge a?tive edge a?tive edge 00 - rising edge 01 - falling edge 10 - both edges 11 - disa?le captu?e xx yy xx yy capture input mode (n=0 or 1) note: 1. ptnm[1:0]=01 and active edge set by the ptnio[1:0] bits 2. a ptmn capture input pin active edge transfers the counter value to ccra 3. ptncclr bit not used 4. no output function C ptnoc and ptnpol bits are not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.10 90 de?e??e? 1?? ?01? rev. 1.10 91 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d converter overview this device contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bi t di gital value. it also can convert the internal signals, the bandgap reference voltage v bg , 10is, usb d+/d- internal divider registers output voltage v dpvdo /v dnvdo , into a 12-bit digital value. the external or internal analog signal to be converted is determined by the sains2~sains0 bits together with the sacs3~sacs0 bits. when the external analog signal is to be converted, the corresponding pin-shared control bits should frst be properly confgured and then desired external channel input should be selected using the sains2~s ains0 and sacs3~sacs0 bits. note that when the internal analog signal is to be converted, the pin-shared control bits should also be properly confgured except the sains and sacs bit felds. more detailed information about the a/d input signal is described in the "a/d converter control registers" and "a/d converter input signals" sections respectively. external input channels internal analog signals channel select bits 8: an0~an ?? vsense 4:v bg ? 10is ? v dpvdo ? v dnvdo sains ? ~sains0 ? sacs ? ~sacs0 the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers. a/d conve?te? start adbz adcen av ss a/ d clo?k ? n (n=0~7) f sys av dd adcen sadol sadoh an1 an ? a/d conve?te? refe?en?e voltage a/d data registe?s v bg adrfs sains?~sains0 sacs?~sacs0 sacks?~ sacks0 vsense 10is v dpvdo v dnvdo pin-sha?ed sele?tion pin-sha?ed sele?tion avdd savrs1~savrs0 vref a/d converter structure
rev. 1.10 9 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 9? de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu a/d converter register description overall operation of the a /d converter is controlled us ing f ve regis ters. a read only regis ter pair exists to store the adc data 12-bit value. the remaining three register s are control registers which setup the operating and control function of the a/d converter. register name bit 7 6 5 4 3 2 1 0 sadol(adrfs=0) d ? d ? d1 d0 sadol(adrfs=1) d7 d ? d5 d4 d ? d ? d1 d0 sadoh(adrfs=0) d11 d10 d9 d8 d7 d ? d5 d4 sadoh(adrfs=1) d11 d10 d9 d8 sadc0 start adbz adcen adrfs sacs ? sacs ? sacs1 sacs0 sadc1 sains ? sains1 sains0 savrs1 savrs0 sacks ? sacks1 sacks0 a/d converter register list a/d converter data registers C sadol, sadoh as the device contains an internal 12-bit a/d converter , it requires two data registers to store the converted value. these are a high byte register , known as sadoh, and a low byte register , known as sadol. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is ut ilised, t he form at i n whi ch t he da ta i s st ored i s c ontrolled by t he adrfs bi t i n t he sadc0 register as shown in the accompanying table. d0~d1 1 are the a/d conversion result data bits. any un used bi ts wi ll be re ad a s z ero. not e t hat t he a/ d c onverter da ta re gister c ontents wi ll be unchanged if the a/d converter is disabled. adrfs sadoh sadol 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d ? d5 d4 d ? d ? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d ? d5 d4 d ? d ? d1 d0 a/d converter data registers a/d converter control registers C sadc0, sadc1 to control the function and operatio n of the a/d converter , two control registers known as sadc0 and sadc1 are provided. these 8-bit registers define functions such as the selection of which analog channel is connected to the internal a/d converter , the digitise d data format, the a/d clock source as well as controlling the start function and monitoring the a/d converter busy status. as the device contains only one actual analog to digital converter hardware circuit, each of the external or i nternal a nalog si gnal i nputs m ust be ro uted t o t he c onverter. t he sacs3~ sacs0 bi ts i n t he sadc0 register are used to determine which external channel input is selected to be converted. the sains2~sains0 bits in the sadc1 register are used to determine that the analog signal to be converted comes from the internal analog signal or external analog channel input. the relev ant pin-shared function selection bits determine which pins on i/o ports are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin- shared function will be removed. in addition, any internal pull-high resistor connected to the pin will be automatically removed if the pin is selected to be an a/d converter input.
rev. 1.10 9? de?e??e? 1?? ?01? rev. 1.10 9 ? de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu ? sadc0 register bit 7 6 5 4 3 2 1 0 na ? e start adbz adcen adrfs sacs ? sacs ? sacs1 sacs0 r/w r/w r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 start : start the a/d conversion 0 1 0: start a/d conversion this bit is used to initiate an a/ d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. bit 6 adbz : a/d converter busy fag 0: a/d conversion ended or no conversion 1: a/d converter is busy this read only fag is us ed to indicate w hether the a /d convers ion is in progress or not. when the st art bit is set from low to high and then to low again, the adbz fag will be set to 1 to indicate that the a/d conversion is initiated. the adbz fag will be cleared as 0 after the a/d conversion is complete. bit 5 adcen : a/d converter enable/disable control 0: disable 1: enable this bit controls the a/d internal function. this bit should be set to one to enable the a/ d c onverter. if t he bi t i s se t l ow, t hen t he a/ d c onverter wi ll be swi tched of f reducing the device power consumption. when the a/d converter function is disabled, the contents of the a/d data register pair known as sadoh and sadol will be unchanged. bit 4 adrfs : a/d output data format selection bit 0: adc output data format sadoh=d[11:4]; sadol=d[3:0] 1: adc output data format sadoh=d[11:8]; sadol=d[7:0] this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d converter data register section. bit 3~0 sacs3~sacs0 : adc input channels selection 0000: adc input channel comes from an0 0001: adc input channel comes from an1 0010: adc input channel comes from an2 0011: adc input channel comes from an3 0100: adc input channel comes from an4 0101: adc input channel comes from an5 0110: adc input channel comes from an6 1000: adc input channel comes from vsense 1001~1111: non-existed channel, the input will be foating if selected ? sadc1 register bit 7 6 5 4 3 2 1 0 na ? e sains ? sains1 sains0 savrs1 savrs0 sacks ? sacks1 sacks0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~5 sains2~sains0 : internal a/d converter input channel selection bit 000: adc input only comes from external pin analog input 001: adc input also comes from internal bandgap reference voltage 010: adc input also comes from internal 10is 011: adc input also comes from internal v dpvdo 100: adc input also comes from internal v dnvdo other values: same as 000
rev. 1.10 94 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 95 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu bit 4~3 savrs1~savrs0 : adc reference voltage selection 00: adc reference voltage only comes from vref 01: adc reference voltage simultaneously comes from vref and a vdd other values: same as 00 bit 2~0 sacks2~sacks0 : adc clock rate selection bit 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: f sys /128 the st art bit in the sadc0 register is used to start the a/d conversion. when the microcontroller sets t his b it f rom l ow t o h igh a nd t hen l ow a gain, a n a nalog t o d igital c onversion c ycle wi ll b e initiated. the adbz bi t i n t he sadc0 re gister i s use d t o i ndicate whe ther t he a nalog t o di gital c onversion process is in progress or not. this bit will be automatically set to 1 by the microcontroller after an a/d conversion is successfully initiated. when the a/d conversion is complete, the adbz will be cleared to 0. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register , and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can poll the adbz bit in the sadc0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter , which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the sacks2~sacks0 bits in the sadc1 register . although the a/d cloc k source is determined by the system clock f sys and by bits sacks2~sacks0, there are some limitations on the maximum a/d clock source speed that can be selected. as the recommended range of permissible a/d clock period, t adck , is from 0.5s to 10s, care must be taken for system clock frequencies. for example, as the system clock operates at a frequency of 8mhz, the sacks2~sacks0 bits should not be set to 000, 001 or 1 11. doing so will give a/d clock periods that are less than the minimum a/d clock period which m ay re sult i n i naccurate a/ d c onversion va lues. re fer t o t he fol lowing t able for e xamples, where values marked with an asteri sk * show where, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period. 1mhz 1s 2s 4s 8s 16s * 32s * 64s * 128s * ? mhz 500ns 1s 2s 4s 8s 16s * 32s * 64s * 4mhz ? 50ns * 500ns 1s 2s 4s 8s 16s * 32s * 8mhz 1 ? 5ns * ? 50ns * 500ns 1s 2s 4s 8s 16s *
rev. 1.10 94 de?e??e? 1?? ?01? rev. 1.10 95 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he adcen bit in the sadc0 register . this bit must be set high to power on the a/d converter . when the adcen bit is set high to power on the a/d converter internal circuitry a certain delay , as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs, if the adcen bit is high, then some power will still be consumed. in power conscious applications it is therefore recommended that the adcen is set low to reduce power consumption when the a/d converter function is not being used. a/d converter reference voltage the reference voltage supply to the a/d converter can be supplied from the positive power supply pin, a vdd, or from an external reference source supplied on pin vref . the desired selection is made using the savrs1 and savrs0 bits. when the savrs bit feld is set to "01", the a/d converter reference volt age will sim ultaneously come from the a vdd pin and vref pin. otherwise, if the savrs bit feld is set to any other value except "01", the a/d converter reference voltage will come from the vref pin. as the a/d converter and usb auto detector d/a converter external reference voltage come from the same vref pin, when the vref pin is selected as the a/d converter reference voltage supply pin, the usb auto detector d/a converter reference voltage selection bit dacvrs bit feld should be also properly confgured except the pin-shared function control bits to avoid f unctional a bnormity. ho wever, i f t he i nternal a/ d c onverter p ower i s se lected a s t he r eference voltage, the vref pin must not be confgured as the reference voltage input function for the a/d converter to avoid the internal connection between the vref pin to a/d converter power a v dd . the analog input value s must not be allo wed to exceed the value of the selected reference voltage, a v dd or v ref . the following table shows how to properly select reference voltage for the a/d converter or usb auto detector d/a converter. a/d converter reference voltage selection usb auto detector reference voltage selection savrs[1:0] dacvrs[1:0] pas01~pas00 avdd avdd 01 00 othe ? s ex ? ept "11" avdd vref 01 01 ? 10 10 vref avdd othe ? s ex ? ept "01" 00 11 vref vref othe ? s ex ? ept "01" 01 ? 10 11 a/d converter input signals all the external a/d analog channel input pins are pin-shared with the i/o pins as well as other functions. the corresponding control bits for each a/d external input pin in the p as0 and p as1 register determine w hether the input pins are s etup as a /d converter analog inputs or w hether they have other functions. if the pin is setup to be as an a/d analog channel input, the original pin functions will be disabled. in this way , pins can be changed under program control to change their function bet ween a/ d inputs and other func tions. al l pull high resi stors, whic h are set up through register programm ing, will be autom atically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the port control register to enable the a/d input as when the pin-shared function control bits enable an a/d input, the status of the port control register will be overridden. there are four internal analog signals derived from the bandgap reference voltage v bg , 10is, and usb d+/d- internal divider registers output voltage v dpvdo /v dnvdo , which can be connected to the a/d converter as the analog input signal by confguring the sains2~sains0 bits. if the external channel input is selected to be converted, the sains2~sains0 bits should be set to "000" and the
rev. 1.10 9 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 97 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu sacs3~sacs0 bits can determine which external channel is selected. if the internal analog signal is selecte d to be converted, the sacs3~sacs0 bits must be confgured with a value from 1000 to 1111 t o swi tch of f t he e xternal a nalog c hannel i nput. ot herwise, t he i nternal a nalog si gnal wi ll be connected together with the external channel input. this will result in unpredictable situations. sains[2:0] sacs[3:0] input signals description 000 ? 101~111 0000~1000 an0~an ?? vsense exte ? nal pin analog input 1001~1111 non-existed channel, input is foating 001 1001~1111 v bg inte ? nal bandgap ? efe ? en ? e voltage 010 1001~1111 10is 10 ti ? es isense input voltage signal 011 1001~1111 v dpvdo usb d+ inte ? nal divide ? ? egiste ? s output voltage 100 1001~1111 v dnvdo usb d- inte ? nal divide ? ? egiste ? s output voltage a/d converter input signal selection conversion rate and timing diagram a com plete a/d conversi on contains two parts, dat a sampli ng and dat a conversion. the dat a sampling which is defned as t ads takes 4 a/d clock cycles and the data conversion takes 12 a/d clock cycles. therefore a total of 16 a/d clock cycles for an external input a/d conversion which is defned as t adc are necessary. maximum single a/d conversion rate=a/d clock period / 16 the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware w ill begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. t he t ime t aken f or t he a/d conversion is 16 t adck clock cycles where t adck is equal to the a/d clock period. adcen start adbz sacs[?:0] (sains[?:0]=000) off on off on t on?st t ads a/d sa?pling ti?e t ads a/d sa?pling ti?e sta?t of a/d ?onve?sion sta?t of a/d ?onve?sion sta?t of a/d ?onve?sion end of a/d ?onve?sion end of a/d ?onve?sion t adc a/d ?onve?sion ti?e t adc a/d ?onve?sion ti?e t adc a/d ?onve?sion ti?e 0011b 0010b 0000b 0001b a/d ?hannel swit?h a/d conversion timing C external channel input
rev. 1.10 9? de?e??e? 1?? ?01? rev. 1.10 97 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d conversion process. ? step 1 select the require d a/d conversion clock by correctly programming bits sacks2~sacks0 in the sadc1 register. ? step 2 enable the a/d converter by setting the adcen bit in the sadc0 register to 1. ? step 3 select which signal is to be connec ted to the internal a/d converter by correctly confguring the sains2~sains0 bits select the external channel input to be converted, go to step 4. select the internal analog signal to be converted, go to step 5. ? step 4 if the a/d converter input signal comes from the external channel input selecting by confguring the sains bit feld, the corresponding pins should be confgured as a/d converter input function by configuring the relevant pin-shared function control bits. the desired analog channel then should be selected by confguring the sacs bit feld. after this step, go to step 6. ? step 5 before the a/d converter input signal is selected to come from the internal analog signal by confguring the sains bit feld, the corresponding external input pin must be switched to a non- existed channel input by setting the sacs3~sacs0 bits with a value from 1001 to 1 111. the desired internal analog signal then can be selected by confguring the sains bit feld. after this step, go to step 6. ? step 6 select the reference voltage source by configuring the sa vrs1~savrs0 bits in the sadc1 register. ? step 7 select a/d converter output data format by setting the adrfs bit in the sadc0 register. ? step 8 if a/d conversion interrupt is used, the interrupt control registers must be correctly confgured to ensure the a/d interrupt function is active. the master interrupt control bit, emi, and the a/d conversion interrupt control bit, ade, must both be set high in advance. ? step 9 the a/d conversion procedure can now be initialized by setting the st art bit from low to high and then low again. ? step 10 if a/ d conversi on i s i n progre ss, t he adbz fla g wi ll be se t high. aft er t he a/ d conversi on process is complete, the a dbz flag w ill go low and then the output data can be read from sadoh and sadol registers. note: when checking for the end of the conversion process, if the met hod of polling the adbz bit in the sadc0 register is used, the interrupt enable step above can be omitted.
rev. 1.10 98 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 99 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu programming considerations during m icrocontroller ope rations where t he a/d c onverter i s not be ing use d, t he a/d i nternal circuitry c an be swi tched of f t o re duce powe r c onsumption, by c learing bi t adce n t o 0 i n t he sadc0 regist er. when thi s happens, the int ernal a/ d converter ci rcuits wi ll not consume power irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/o pins, then care must be taken as if the input voltag e is not at a valid logic level, then this may lead to some increase in power consumption. a/d conversion function as the device contains a 12-bit a/d converter , its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the actual a/d converter reference voltage, v ref , this gives a single bit analog input value of v ref divided by 4096. 1 lsb=v ref 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage=a/d output digital value v ref 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the v ref level. note that here the v ref voltage is the actual a/d converter reference voltage determined by the savrs feld. fffh ffeh ffdh 0?h 0?h 01h 0 1 ? ? 409? 4094 4095 409? v ref 409? analog input voltage a/d conversion result 1.5 lsb 0.5 lsb ideal a/d transfer function
rev. 1.10 98 de?e??e? 1?? ?01? rev. 1.10 99 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu a/d conversion programming examples the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the adbz bit in the sadc0 register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an adbz polling method to detect the end of conversion clr a de ; disable adc interrupt mov a,03h mov sa dc1,a ; select f sys /8 as a/d clock set a dcen mov a, 0ch ; setup pas0 to confgure pin an0 mov p as0,a mov a,20h mov s adc0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr st art ; high pulse on start bit to initiate conversion set s tart ; reset a/d clr s tart ; start a/d polling_eoc: sz a dbz ; poll the sadc0 register adbz bit to detect end of a/d conversion jmp p olling_eoc ; continue polling mov a ,sadol ; read low byte conversion result value mov s adol_buffer,a ; save result to user defned register mov a ,sadoh ; read high byte conversion result value mov s adoh_buffer,a ; save result to user defned register : : jmp s tart_conversion ; start next a/d conversion
rev. 1.10 100 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 101 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu example: using the interrupt method to detect the end of conversion clr a de ; disable adc interrupt mov a,03h mov sa dc1,a ; select f sys /8 as a/d clock set a dcen mov a, 0ch ; setup pas0 to confgure pin an0 mov p as0,a mov a,20h mov s adc0,a ; enable and connect an0 channel to a/d converter start_conversion: clr st art ; high pulse on start bit to initiate conversion set s tart ; reset a/d clr s tart ; start a/d clr a df ; clear adc interrupt request fag set a de ; enable adc interrupt set e mi ; enable global interrupt : : ; adc interrupt service routine adc_isr: mov ac c_stack,a ; save acc to user defned memory mov a ,status mov s tatus_stack,a ; save status to user defned memory : : mov a ,sadol ; read low byte conversion result value mov s adol_buffer,a ; save result to user defned register mov a ,sadoh ; read high byte conversion result value mov s adoh_buffer,a ; save result to user defned register : : exit_int_isr: mov a ,status_stack mov s tatus,a ; restore status from user defned memory mov a ,acc_stack ; restore acc from user defned memory reti
rev. 1.10 100 de?e??e? 1?? ?01? rev. 1.10 101 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu usb auto detection the device includes one usb port named d0+/d0- to implement the usb device auto detection function. users can distinguish that the device connected to the usb port is a dedicated char ger, portable device, general usb interface or char ging device with usb interface by monitoring the voltage and current of the connected usb lines. d- dnplen m u x pa? m u x vdd 8-?it dac1 dac1en aduda1[7:0] d+ dpplen m u x pas0[7:?] pa1 8-?it dac0 dac0en aduda0[7:0] usw pas0[?:?] dacvrs[1:0] dpsw d+_r1 d+_r? dnsw d-_r1 d-_r? dnvdo dpvdo vref (to a/d inte?nal input) (to a/d inte?nal input) usb auto detection block diagram usb auto detection the d+/d- usb ports are used for usb auto detection. these two pins are pin-shared with normal i/o function, a/d input function, which are determined by the related pin-shared control bits. there two 8-bit d/a converters, dac0 and dac1, which are repectiv ely enabled by the dac0en and dac1en bits in the aduc0 register . the d/a converter output signal is controlled by the adudan register value and the reference voltage which is selected by the dacvrs1~dacvrs0 bits i n t he aduc 0 r egister. t here i s a n a nalog swi tch c onnected b etween t he d+ a nd d- l ines, which is controlle d by the usw bit. note that only when one of the d+ and d- pins is confgur ged as analog or digita l input by setting the related pin-shared control bits as well as the usw bit is set high, can the switch be on. the d+ and d- lines are individually connected a pull-low resistor to vss, which are repectively controlled by the dpplen and dnplen bits in the aduc0 register . the d+ a nd d- pi ns ha ve t wo i nternal resistor di viders , d+_r1 /d+_r2 a nd d-_r1/ d-_r2, whi ch are controlled by the d psw and d nsw bits . the voltage generated on each group of divider registers can be used as an internal analog input signal for the a/d converter.
rev. 1.10 10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 10? de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu usb auto detection registers overall operation of the usb auto detection function is controlled using several registers. register name bit 7 6 5 4 3 2 1 0 aduc0 usw dacvrs1 dacvrs0 dnplen dpplen dac1en dac0en aduc1 dnsw dpsw aduda0 d7 d ? d5 d4 d ? d ? d1 d0 aduda1 d7 d ? d5 d4 d ? d ? d1 d0 usb auto detection registers list aduc0 register bit 7 6 5 4 3 2 1 0 na ? e usw dacvrs1 dacvrs0 dnplen dpplen dac1en dac0en r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 usw : usw switch on/off control 0: off 1: on note that only when one of the d+ and d- pins is confgured as analog or digital input by setting the rela ted pin-shared control bits as well as the usw bit is set high, can the switch be on. bit 6 unimplemented, read as "0" bit 5~4 dacvrs1~dacvrs0 : dac0 and dac1 reference voltage selection 00: from vdd pin 01: from vref pin 10: from vref pin 11: undefned bit 3 dnplen : d- pin pull-low disable/enable control 0: disable 1: enable bit 2 dpplen : d+ pin pull-low disable/enable control 0: disable 1: enable bit 1 dac1en : dac1 disable/enable control 0: disable 1: enable bit 0 dac0en : dac0 disable/enable control 0: disable 1: enable aduc1 register bit 7 6 5 4 3 2 1 0 na ? e dnsw dpsw r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1 dnsw : d- internal registers disable/enable control 0: disable 1: enable bit 0 dpsw : d+ internal registers disable/enable control 0: disable 1: enable
rev. 1.10 10? de?e??e? 1?? ?01? rev. 1.10 10 ? de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu aduda0 register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : 8-bit dac0 output control data bits dac0 output=(dac0 reference v oltage)(aduda0[7:0])/256 aduda1 register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : 8-bit dac1 output control data bits dac1 output=(dac1 reference v oltage)(aduda1[7:0])/256 battery charge module the device contains a batt ery char ge module which consi sts of circuitry for battery char ging constant current (cc) or constant voltage (cv) modes a s well as ovp and ocp functions. the constant current sense signal is from isense pin while the constant voltage signal is from the vsense pin. the ovp or ocp circuitry uses external pins, named vsense, isense, and cp0n, to detect 10is voltage or vs voltage and this output voltage is used to modify the duty of the current ode pwm controller to control the charging current and charging voltage. rectifier/ filter/ regulator 10 is vs sensein current mode pwm controller dac isense 3v 5v pgd a1n a1x opa0 opa1 ovp ocp bat. 5v cp0n vsense ch1 ch0 9r r hv mux cmp1 cmp0 battery charge module structure note: 1.the input voltage range of isense should be less than 0.36v at 5v. 2. when the vsense voltage is than 3v and v is than or equal to 4.6v , then the ovp output is high, an ocvp interrupt occurs and the a1x pin will output a low level. 3. when the 10is voltage is than cp0n and v is than or equal to 4.6v , the ocp output is high, ocvp interrupt occurs and the a1x pin will output a low level.
rev. 1.10 104 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 105 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu battery charging constant current and constant voltage modes the battery char ging current is mea sured using a resistor to produce a voltage which is input to the opa0 via isense pin. then the isense voltage is amplifed 10 times by op a0 to produce a 10is voltage. this voltage is input to mux channel 1 and an a/d converter internal channel. when mu x select s ch 1 from the 10is voltage and the opa1 pos itive voltage comes from the dac, if the 10is voltage is less than the dac voltage, the a1x output signal is transmitted to the current mode pwm controller via a photo-coupler to indirectly increase pwm duty cycle of the power mos driving port of the current mode pwm control circuits. the battery char ging voltage is meas ured us ing external tw o res istors to produce a voltage w hich is input to the mux via the vsense pin. this voltage is the same as vs. when the mux channel selects ch0, the vs voltage will be sent out via the sensein pin and the external resister to the opa1 negative input. as the op a1 non-inverting input is from the 12-bit dac input, use the dac value to determine the battery char ging voltage, because the opa1 output , a1x, transmit s the v s and dac dif ference via a photo-coupler to the current mode pwm controller . i f the vs voltage is less than the dac voltage, a1x is transmitted to the current mode pwm controller via a photo- coupler to indirectly increases the pwm duty cycle of the power mos driving port of the current mode pwm control circuits. ocp and ovp functions the ocp function is used to monitor the battery char ging current, which is converted to a voltage using a resistor . the voltage signal is input to op a0 via the isense pin. then the isense voltage is amplifed 10 t imes by a n op a0 t o produc e a 10is vol tage. if the 10is vol tage i s greater t han cp0n and pgd (power good detection) it means that the device power supply is ready , v dd i s greater than or equal to 4.6v , an ocvp interrupt will occur when the corresponding int errupt is enabled and will force the a1x output l ow. the ovp function is used to monitor the battery char ging voltage, which is converted to a voltage using two external resistors, and the voltage is input to the vsense pin. if the vsense pin input voltage i s greater t han 3v a nd pgd (power goo d de tection) , t his m eans t hat t he de vice po wer supply is ready , v dd is greater than or equal to 4.6v , an ocvp interrupt will occur when the corresponding interrupt is enabled and will force the a1x output l ow. pgdr register bit 7 6 5 4 3 2 1 0 na ? e pgdf r/w r por 0 bit 7~1 unimplemented, read as "0" bit 0 : power good detection ready fag 0: detect v dd <4.6v 1: detect v dd 4.6v note: the device can detect the v dd current status by pgdf bit.
rev. 1.10 104 de?e??e? 1?? ?01? rev. 1.10 105 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu battery charge module registers the overall battery char ge function is controlled by several registers and the corresponding register defnitions are described in the accompanying sections. register name bit 7 6 5 4 3 2 1 0 chrgen chgen7 chgen ? chgen5 chgen4 chgen ? chgen ? chgen1 chgen0 dacl d7 d ? d5 d4 d ? d ? d1 d0 dach d11 d10 d9 d8 dacc endac sensw muxs5 muxs4 muxs ? muxs ? muxs1 muxs0 a0vos a0fm a0rsp a0x a0of4 a0of ? a0of ? a0of1 a0of0 pgdr pgdf battery charge module registers list chrgen register bit 7 6 5 4 3 2 1 0 na ? e chgen7 chgen ? chgen5 chgen4 chgen ? chgen ? chgen1 chgen0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 chgen7~chgen0 : mux, dac and opa0 related control registers modifcation 10101010: the related registers could be modifed other values: ignore registers modify when these bits are changed to any other values except 10101010, the dacl, dach, dacc, sensw and a0vos registers cannot be modifed. digital to analog converter the ba ttery c harge m odule c ontains a 12- bit dac. t he dac i s use d t o se t a re ference c harging current or reference charging voltage using the dacl and dach registers. d[11:0] r?r 1?-?it dac endac s0 - + opa1 vdd pa7/a1p dac note : 1. the endac has an interlocking relationship with s0 when endac=0, the dac is disable d and s0 is off. when endac=1, the dac enable d and s0 is on. 2. the opa1 positive input voltage can be selected from an external pin which is named a1p .
rev. 1.10 10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 107 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu dacl register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : dac output control data bits note: w rit to this register only write s to a shadow buf fer . w riting to the dach register will also copy the shadow buffer data to the dacl register. dach register bit 7 6 5 4 3 2 1 0 na ? e d11 d10 d9 d8 r/w r/w r/w r/w r/w por 1 0 0 0 bit 7~4 unimplemented, read as "0" bit 3~0 d1 1 ~ d8 : dac output control data bits, only for 12 bits dac note: the 12-bit dac data should be first written to dacl then data written to dach to allow dac can operate normally. 12-bit dac output voltage=(d[11:0]/2 12 ) v dacc register bit 7 6 5 4 3 2 1 0 na ? e endac r/w r/w por 1 bit 7 endac : dac and s0 control 0: dac disable & s0 off 1: dac enable & s0 on bit 6~0 unimplemented, read as "0" operational amplifer 0 the battery char ge module contains an operational amplifier 0, which is onl used in the attery charging constant current mode. v dd =5v 0.1v - + ?v(ovp) isense vm s0 s1 s? 9r r opa0 ch1 ch0 a0fm a0x
rev. 1.10 10? de?e??e? 1?? ?01? rev. 1.10 107 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu sensw register bit 7 6 5 4 3 2 1 0 na ? e muxs5 muxs4 muxs ? muxs ? muxs1 muxs0 r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 bit 7~6 unimplemented, read as "0" bit 5~0 muxs5~muxs0 : mux channel selection 010101: ch0 (switch to vsense pin input) 101010: ch1 (switch to opa0 input) other values: keep the current switch state unchanged. for example, when the mux[5:0]=101010, switch to ch1, but when mux[5:0] are changed to 1 11111, switch state, ch1, is unchanged, till when the mux[5:0] is set to 010101, switch state will be changed to ch0. a0vos register bit 7 6 5 4 3 2 1 0 na ? e a0fm a0rsp a0x a0of4 a0of ? a0of ? a0of1 a0of0 r/w r/w r/w r r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 a0fm : operational amplifer mode or offset calibration mode 0: operational amplifer mode (s1 off and s2 on) 1: offset calibration mode (s1 on and s2 off) bit 6 a0rsp : operational amplifer input voltage selection bit 0: input voltage comes from isense pin 1: input voltage comes from internal vm reference voltage bit 5 a0x : operational amplifer output; positive logic. this bit is read only. bit 4~0 a0of4~a0of0 : operational amplifer offset calibration data bits opa0 functions the op a0 can operate together with the mux, dac and op a1 as shown in the main functional blocks of the battery charging circuit. the op a0 provides its input voltage of fset to be adjustable by using common mode input to calibrate the offset. the calibration steps are as following: ? set a0fm=1 to setup the offset cancellation mode, here s1 on and s2 off. ? set a0rsp to select which input pin is to be used as the reference voltage C isense pin or vm. ? adjust a0of4~a0of0 until the output status changes ? set a0fm=0 to restore the normal comparator mode. note: 1. when calibration, the device can detect the opa output status by a0x bit. 2. vm voltage is 0.1v at v = 5 v. 3. after opa0 offset calibration, set the a0rsp bit by the actual applications.
rev. 1.10 108 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 109 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu scom function for lcd the device has the capability of driving external lcd panels. the common pins for lcd driving, scom0~scom3, are pin shared with the i/o pins. the lcd signals (com and seg) are generated using the application program. lcd operation an external lcd panel can be driven us ing this device by configuring the i/o pins as common pins and confguring the i/o pins as segment pins. the lcd driver function is controlled using the scomc regis ter w hich in addition to controlling the overall on/of f function als o controls the bias voltage setup function. this enables the lcd com driver to generate the necessary v dd /2 voltage levels for lcd 1/2 bias operation.
lcd com bias the s comen bit in the s comc register is the overall mas ter control for the lcd driver . the lcd scomn pin is selected to be used for lcd driving by the corresponding pin-shared function selection bits. note that the port control register does not need to frst setup the pins as outputs to enable the lcd driver operation. lcd bias current control the lcd com driver enables a range of selections to be provided to suit the requirement of the lcd panel which is being used. the bias resistor choice is implemented using the isel1 and isel0 bits in the scomc register. scomc register bit 7 6 5 4 3 2 1 0 na ? e isel1 isel0 scomen r/w r/w r/w r/w por 0 0 0 bit 7 unimplemented, read as "0" bit 6~5 : select resistor for r type lcd bias current 00: 2100k (1/2 bias), i bias= 25a@(v dd =5v) 01: 250k (1/2 bias), i bias =50a@(v dd =5v) 10: 225k (1/2 bias), i bias= 100a@(v dd =5v) 11: 212.5k (1/2 bias), i bias =200a@(v dd =5v) bit 4 : lcd control bit 0: off 1: on when scomen is set, it will turn on the dc path of resistor to generate 1/2 v dd bias voltage. bit 3~0 unimplemented, read as "0"
rev. 1.10 108 de?e??e? 1?? ?01? rev. 1.10 109 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the m icrocontroller t o d irect a ttention t o t heir r espective n eeds. t he d evice c ontains o ne e xternal interrupt and internal interrupts functions. the external interrupt is generated by the action of the external intn pin, while the internal interrupts are generated by various internal functions such as the tms, t ime base, eeprom, ocvp, lvd and the a/d converter. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the special purpose data memory , as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. the frst is the intc0~intc2 regist ers which setup the primary interrupt, the second is the mfi0~mfi2 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each regist er contai ns a number of enable bit s to enable or disa ble indivi dual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "e" for enable/disable bit or "f" for request fag. function enable bit request flag notes glo ? al emi intn pin intne intnf n=0 o ? 1 ti ? e base tbne tbnf n=0 o ? 1 multi-fun ? tion mfne mfnf n=0~ ? ocvp fun ? tion ocvpf ocvpe lvd lve lvf eeprom dee def a/d conve ? te ? ade adf tm stmae stmaf stmpe stmpf ptmnae ptmnaf n=0 o ? 1 ptmnpe ptmnpf interrupt register bit naming conventions register name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 mf0f tb0f int0f mf0e tb0e int0e emi intc1 tb1f adf def ocvpf tb1e ade dee ocvpe intc ? lvdf mf ? f mf1f int1f lvde mf ? e mf1e int1e mfi0 stmaf stmpf stmae stmpe mfi1 ptm0af ptm0pf ptm0ae ptm0pe mfi ? ptm1af ptm1pf ptm1ae ptm1pe interrupt registers list
rev. 1.10 110 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 111 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu integ register bit 7 6 5 4 3 2 1 0 na ? e int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as "0" bit 3~2 int1s1~int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: both rising and falling edges bit 1~0 int0s1~int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: both rising and falling edges intc0 register bit 7 6 5 4 3 2 1 0 na ? e mf0f tb0f int0f mf0e tb0e int0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 mf0f : multi-function 0 interrupt request fag 0: no request 1: interrupt request bit 5 tb0f : t ime base 0 interrupt request fag 0: no request 1: interrupt request bit 4 int0f : int0 interrupt request fag 0: no request 1: interrupt request bit 3 mf0e : multi-function 0 interrupt control 0: disable 1: enable bit 2 tb0e : t ime base 0 interrupt control 0: disable 1: enable bit 1 int0e : int0 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable
rev. 1.10 110 de?e??e? 1?? ?01? rev. 1.10 111 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu intc1 register bit 7 6 5 4 3 2 1 0 na ? e tb1f adf def ocvpf tb1e ade dee ocvpe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tb1f : t ime base 1 interrupt request fag 0: no request 1: interrupt request bit 6 adf : a/d converter interrupt request fag 0: no request 1: interrupt request bit 5 def : data eeprom interrupt request fag 0: no request 1: interrupt request bit 4 ocvpf : ocvp interrupt request fag 0: no request 1: interrupt request bit 3 tb1e : t ime base 1 interrupt control 0: disable 1: enable bit 2 ade : a/d converter interrupt control 0: disable 1: enable bit 1 dee : data eeprom interrupt control 0: disable 1: enable bit 0 ocvpe : ocvp interrupt control 0: disable 1: enable intc2 register bit 7 6 5 4 3 2 1 0 na ? e lvdf mf ? f mf1f int1f lvde mf ? e mf1e int1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 lvdf : lvd interrupt request fag 0: no request 1: interrupt request bit 6 mf2f : multi-function 2 interrupt request fag 0: no request 1: interrupt request bit 5 mf1f : multi-function 1 interrupt request fag 0: no request 1: interrupt request bit 4 int1f : int1 interrupt request fag 0: no request 1: interrupt request bit 3 lvde : lvd interrupt control 0: disable 1: enable
rev. 1.10 11 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 11 ? de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu bit 2 mf2e : multi-function 2 interrupt control 0: disable 1: enable bit 1 mf1e : multi-function 1 interrupt control 0: disable 1: enable bit 0 int1e : int1 interrupt control 0: disable 1: enable mfi0 register bit 7 6 5 4 3 2 1 0 na ? e stmaf stmpf stmae stmpe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 stmaf : stm comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 stmpf : stm comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 stmae : stm comparator a match interrupt control 0: disable 1: enable bit 0 stmpe : stm comparator p match interrupt control 0: disable 1: enable mfi1 register bit 7 6 5 4 3 2 1 0 na ? e ptm0af ptm0pf ptm0ae ptm0pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 ptm0af : ptm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 ptm0pf : ptm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 ptm0ae : ptm0 comparator a match interrupt control 0: disable 1: enable bit 0 ptm0pe : ptm0 comparator p match interrupt control 0: disable 1: enable
rev. 1.10 11 ? de?e??e? 1?? ?01? rev. 1.10 11 ? de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu mfi2 register bit 7 6 5 4 3 2 1 0 na ? e ptm1af ptm1pf ptm1ae ptm1pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 ptm1af : ptm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 ptm1pf : ptm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 ptm1ae : ptm1 comparator a match interrupt control 0: disable 1: enable bit 0 ptm1pe : ptm1 comparator p match interrupt control 0: disable 1: enable interrupt operation when the conditions for an interrupt event occur , such as a tm comparator p , comparator a match or a/d conversion completion etc., the relevant interrupt request f ag will be set. whether the request f ag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. if the enable bit is set high then the program will jump to its r elevant v ector, i f t he e nable b it i s z ero t hen a lthough t he i nterrupt r equest f ag i s se t a n a ctual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a "jmp" which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a "reti", which retrieves the original program counter address from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying di agrams with their order of priority . som e interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . o nce an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request f ag will still be recorded.
rev. 1.10 114 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 115 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. al l o f t he i nterrupt r equest f ags wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode wi th t he e xception of t he ov er v oltage/current c ondition i n t he sl eep mo de a s t he wdt disable. however , to prevent a wake-up from occurring the corresponding f ag should be set before the device is in sleep or idle mode. int0 pin m. fun?t. 1 int0f mf1f int0e mf1e emi 04h emi 08h emi 0ch emi 10h ti?e base 1 tb1f tb1e emi 1ch inte??upt na?e request flags ena?le bits maste? ena?le vector emi auto disa?led in isr p?io?ity high low m. fun?t. 0 mf0f mf0e inte??upts ?ontained within multi-fun?tion inte??upts xxe ena?le bits xxf request flag? auto ?eset in isr legend xxf request flag? no auto ?eset in isr emi ?0h emi ?4h ti?e base 0 tb0f tb0e ocvp ocvpf ocvpe int1 pin int1f int1e a/d ?onve?te? adf ade emi 18h emi 14h eeprom def dee lvd lvf lve emi ?8h emi ?ch m. fun?t. ? mf?f mf?e stm p stmpf stmpe stm a stmaf stmae ptm0 p ptm0pf ptm0pe ptm0 a ptm0af ptm0ae ptm1 p ptm1pf ptm1pe ptm1 a ptm1af ptm1ae interrupt structure
rev. 1.10 114 de?e??e? 1?? ?01? rev. 1.10 115 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu external interrupt the external interrupts are controlled by signal transitions on the pins int0~int1. an external interrupt request will take place when the external interrupt request fags, int0f~int1f , are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins . t o allow the program to branch to its res pective interrupt vector addres s, the g lobal i nterrupt e nable b it, e mi, a nd r espective e xternal i nterrupt e nable b it, i nt0e~int1e, must first be set. additionally the correct interrupt edge type mus t be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be confgured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set and the external interrupt pin is selected by the corresponding pin-shared function selection bits. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the external interrupt request fags, int0f~int1f , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ re gister i s use d t o se lect t he t ype of a ctive e dge t hat wi ll t rigger t he e xternal i nterrupt. a choice of ei ther risi ng or fall ing or both edge types ca n be chosen to tri gger an ext ernal int errupt. note that the integ register can also be used to disable the external interrupt function. ocvp interrupt the ocvp interrupt is controlled by the two internal comparators. an ocvp interrupt request will take pl ace whe n t he oc vp i nterrupt re quest fa g, oc vpf, i s se t, a si tuation t hat wi ll oc cur whe n the comparators output changes state. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and ocvp interrupt enable bit, ocvpe, must frst be set. when the interrupt is enabled, the stack is not full and the comparator input generates a comparator output transition, a subroutine call to the ocvp interrupt vector , will take place. when the ocvp interrupt is serviced, the emi bit will be automatically clear ed to disable other interrupts, and the ocvp interrupt request fag, ocvpf, will also be automatically cleared. time base interrupts the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the t ime base overfow s, a subroutine call to their res pective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the t ime base interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section.
rev. 1.10 11 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 117 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu tbc register bit 7 6 5 4 3 2 1 0 na ? e tbon tbck tb11 tb10 tb0 ? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 tbon : tb0 and tb1 control bit 0: disable 1: enable bit 6 tbck : select f clock 0: f tbc 1: f /4 bit 5~4 tb1 1 ~ tb10 : select t ime base 1 t ime-out period 00: 2 12 /f 01: 2 13 /f 10: 2 14 /f 11: 2 15 /f bit 3 unimplemented, read as "0" bit 2~0 tb02 ~ tb00 : select t ime base 0 t ime-out period 000: 2 /f 001: 2 /f 010: 2 10 /f 011: 2 11 /f 100: 2 12 /f 101: 2 13 /f 110: 2 14 /f 111: 2 15 /f

time base interrupt a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/ d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector a ddress, the global interrupt enable bit, emi, a nd a/ d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts.
rev. 1.10 11 ? de?e??e? 1?? ?01? rev. 1.10 117 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu lvd interrupt an l vd interrupt reques t w ill take place w hen the l vd interrupt reques t f ag, l vf, is s et, w hich occurs when the low v oltage detector function detects a low power supply voltage. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and low v oltage interrupt enable bit, l ve, must frst be set. when the inte rrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the l vd interrupt vector , will take place. when the low v oltage interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, and the lvd interrupt request fag, lvf, will be also automatically cleared. eeprom interrupt an eeprom interrupt request will take place when the eeprom interrupt request fag, def, is set, which occurs when an eeprom w rite cycle ends. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and eeprom interrupt enable bit, dee, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom w rite cycle ends, a subroutine call to the respective eeprom interrupt vect or, will take place. when the eeprom interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, and the eeprom interrupt request fag, def, will also be automatically cleared. multi-function interrupts within this device there are up to three multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts. a multi-function interrupt request will take place when any of the multi-function interrupt request flags, mfnf are set. the multi-function interrupt flags will be set when any of their included functions generate an interrupt request fag. t o allow the program to branch to its respective interrupt vector address, when the multi-func tion interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, i t m ust be not ed t hat, a lthough t he mul ti-function int errupt fa gs wi ll be a utomatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the tm interrupts will not be automatically reset and must be manually reset by the application program. tm interrupts the s tandard and p eriodic tm s have tw o interrupts , one comes from the comparator a match situation and the other comes from the comparator p match situation. all of the tm interrupts are contained within the multi-function interrupts. for all of the tm types there are two interrupt request fags and two enable control bits. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p or a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts. however , only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program.
rev. 1.10 118 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 119 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu interrupt wake-up function each of the int errupt funct ions has the ca pability of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pin, a low power supply voltage or comparator input change may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no ef fect on the interrupt wake-up function. programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the multi-function interrupt request flags, mfnf , will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the "call" instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n sl eep o r i dle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.10 118 de?e??e? 1?? ?01? rev. 1.10 119 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu low voltage detector C lvd the device has a low v oltage detector function, also known as l vd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low v oltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name l vdc. three bits in this register , vl vd2~vlvd0, are used to select one of eight fxed voltages below which a low voltage conditionwill be determined. a low voltage condition is indicated when the l vdo bit is set. if the l vdo bit is low , this indicates that the v dd voltage is above the pres et low voltage value. the enl vd bit is used to control the overall on/of f function of the low voltage detector . setting the bit high will enable the low voltage detector . clearing the bit to zero will switch of f the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 na ? e lvdo enlvd vbgen vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 : lvd output flag 0: no low v oltage detect 1: low v oltage detect bit 4 : low v oltage detector control 0: disable 1: enable bit 3 : bandgap buffer control 0: disable 1: enable note that the bandgap circuit is enabled when the l vd or l vr functio n is enabled or when the vbgen bit is set to 1. bit 2~0 : select lvd v oltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v
rev. 1.10 1 ? 0 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?1 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu lvd operation the low v oltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed volta ge level stored in the l vdc register . this has a range of between 2.0v and 4.0v . when the power supply voltage, v dd , falls below this pre-determined value, the l vdo bit will be set high indicating a low power supply voltage condition. the low v oltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is in the sleep mode, the low voltage detector will be disabled even if the enl vd bit is high. after enabling the low v oltage detector , a time delay t lvds should be allowed for the circuitry to stabilise before reading the l vdo bit. note also that as the v dd voltage may rise and fall rather slowly , at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. vdd enlvd lvdo v lvd t lvds lvd operation the low v oltage detector also has its own interrupt, providing an alte rnative means of low voltage detection, in addit ion to polling the l vdo bit. the interrupt will only be generated after a delay of t lvd after the l vdo bit has been set high by a low voltage condition. when the device is powered down the low v oltage detector will remain active if the enl vd bit is high. in this case, the l vf interrupt request fag will be set, causing an interrupt to be generated if v dd falls below the preset lvd v oltage. t his wi ll c ause t he d evice t o wa ke-up f rom t he sl eep o r i dle mo de, h owever i f the low v oltage detector wake up function is not required then the l vf fag should be frst set high before the device enters the sleep or idle mode. when l vd functi on is enabled, it is recommenced to clear l vd fag frst, and then enables interrupt function to avoid mistake action.
rev. 1.10 1?0 de?e??e? 1?? ?01? rev. 1.10 1 ? 1 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu application circuits usb auto detector rectifier/ filter/ regulator qc2.0 : (5v, 9v, 12v, 20v@2a) 10xis vs sensein dac isense pgd a1n opa0 opa1 ovp ocp ch1 ch0 mux a1x vsense cp0n 5v vss pa4 pb0 pb7 pc0 pc3 5v current mode pwm controller 5v ldo hv 5v HT45F5R battery charge (support qc2.0 ) usb connector usb+ d- d+ usb- 510k pa0 d- d+ 3v qc2.0 detection hv vdd pa6 pa7 pa5 0.1ohm 100k 100k 0.1uf 470 cmp1 cmp0
rev. 1.10 1 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?? de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.10 1?? de?e??e? 1?? ?01? rev. 1.10 1 ?? de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been carried out. this is done by placing a return ins truction " ret" in the s ubroutine w hich w ill cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is take n care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be set as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "hal t" i nstruction f or po wer-down o perations a nd i nstructions t o c ontrol t he o peration o f the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.10 1 ? 4 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?5 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [ ? ] add data me ? o ? y to acc 1 z ? c ? ac ? ov addm a ? [ ? ] add acc to data me ? o ? y 1 note z ? c ? ac ? ov add a ? x add i ?? ediate data to acc 1 z ? c ? ac ? ov adc a ? [ ? ] add data me ? o ? y to acc with ca ?? y 1 z ? c ? ac ? ov adcm a ? [ ? ] add acc to data ? e ? o ? y with ca ?? y 1 note z ? c ? ac ? ov sub a ? x su ? t ? a ? t i ?? ediate data f ? o ? the acc 1 z ? c ? ac ? ov sub a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc 1 z ? c ? ac ? ov subm a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ? esult in data me ? o ? y 1 note z ? c ? ac ? ov sbc a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ca ?? y 1 z ? c ? ac ? ov sbcm a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ca ?? y ? ? esult in data me ? o ? y 1 note z ? c ? ac ? ov daa [ ? ] de ? i ? al adjust acc fo ? addition with ? esult in data me ? o ? y 1 note c logic operation and a ? [ ? ] logi ? al and data me ? o ? y to acc 1 z or a ? [ ? ] logi ? al or data me ? o ? y to acc 1 z xor a ? [ ? ] logi ? al xor data me ? o ? y to acc 1 z andm a ? [ ? ] logi ? al and acc to data me ? o ? y 1 note z orm a ? [ ? ] logi ? al or acc to data me ? o ? y 1 note z xorm a ? [ ? ] logi ? al xor acc to data me ? o ? y 1 note z and a ? x logi ? al and i ?? ediate data to acc 1 z or a ? x logi ? al or i ?? ediate data to acc 1 z xor a ? x logi ? al xor i ?? ediate data to acc 1 z cpl [ ? ] co ? ple ? ent data me ? o ? y 1 note z cpla [ ? ] co ? ple ? ent data me ? o ? y with ? esult in acc 1 z increment & decrement inca [ ? ] in ?? e ? ent data me ? o ? y with ? esult in acc 1 z inc [ ? ] in ?? e ? ent data me ? o ? y 1 note z deca [ ? ] de ?? e ? ent data me ? o ? y with ? esult in acc 1 z dec [ ? ] de ?? e ? ent data me ? o ? y 1 note z rotate rra [ ? ] rotate data me ? o ? y ? ight with ? esult in acc 1 none rr [ ? ] rotate data me ? o ? y ? ight 1 note none rrca [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y with ? esult in acc 1 c rrc [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y 1 note c rla [ ? ] rotate data me ? o ? y left with ? esult in acc 1 none rl [ ? ] rotate data me ? o ? y left 1 note none rlca [ ? ] rotate data me ? o ? y left th ? ough ca ?? y with ? esult in acc 1 c rlc [ ? ] rotate data me ? o ? y left th ? ough ca ?? y 1 note c
rev. 1.10 1?4 de?e??e? 1?? ?01? rev. 1.10 1 ? 5 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu mnemonic description cycles flag affected data move mov a ? [ ? ] move data me ? o ? y to acc 1 none mov [ ? ] ? a move acc to data me ? o ? y 1 note none mov a ? x move i ?? ediate data to acc 1 none bit operation clr [ ? ].i clea ? ? it of data me ? o ? y 1 note none set [ ? ].i set ? it of data me ? o ? y 1 note none branch operation jmp add ? ju ? p un ? onditionally ? none sz [ ? ] skip if data me ? o ? y is ze ? o 1 note none sza [ ? ] skip if data me ? o ? y is ze ? o with data ? ove ? ent to acc 1 note none sz [ ? ].i skip if ? it i of data me ? o ? y is ze ? o 1 note none snz [ ? ].i skip if ? it i of data me ? o ? y is not ze ? o 1 note none siz [ ? ] skip if in ?? e ? ent data me ? o ? y is ze ? o 1 note none sdz [ ? ] skip if de ?? e ? ent data me ? o ? y is ze ? o 1 note none siza [ ? ] skip if in ?? e ? ent data me ? o ? y is ze ? o with ? esult in acc 1 note none sdza [ ? ] skip if de ?? e ? ent data me ? o ? y is ze ? o with ? esult in acc 1 note none call add ? su ?? outine ? all ? none ret retu ? n f ? o ? su ?? outine ? none ret a ? x retu ? n f ? o ? su ?? outine and load i ?? ediate data to acc ? none reti retu ? n f ? o ? inte ?? upt ? none table read operation tabrd [ ? ] read table (specifc page) to tblh and data memory ? note none tabrdc [ ? ] read ta ? le ( ? u ?? ent page) to tblh and data me ? o ? y ? note none tabrdl [ ? ] read ta ? le (last page) to tblh and data me ? o ? y ? note none miscellaneous nop no ope ? ation 1 none clr [ ? ] clea ? data me ? o ? y 1 note none set [ ? ] set data me ? o ? y 1 note none clr wdt clea ? wat ? hdog ti ? e ? 1 to ? pdf clr wdt1 p ? e- ? lea ? wat ? hdog ti ? e ? 1 to ? pdf clr wdt ? p ? e- ? lea ? wat ? hdog ti ? e ? 1 to ? pdf swap [ ? ] swap ni ?? les of data me ? o ? y 1 note none swapa [ ? ] swap ni ?? les of data me ? o ? y with ? esult in acc 1 none halt ente ? powe ? down ? ode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the "clr wdt1" and " clr wdt2" ins tructions the t o and pdf flags may be af fected by the execution status. the t o and pdf flags are cleared after both "clr wdt1" and "clr wdt2" instructions are consecutively executed. otherwise the t o and pdf fags remain unchanged.
rev. 1.10 1 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?7 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
rev. 1.10 1?? de?e??e? 1?? ?01? rev. 1.10 1 ? 7 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt1 pre-clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re a ll c leared. n ote t hat t his instruction w orks in conjunction w ith c lr w dt2 a nd m ust b e e xecuted al ternately w ith c lr w dt2 to h ave effect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt2 w ill have no e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt2 pre-clear w atchdog t imer description the t o, p df f ags and t he w dt are all cleared. n ote t hat t his i nstruction w orks i n conjunction with c lr w dt1 a nd m ust b e e xecuted al ternately w ith c lr w dt1 to h ave e ffect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt1 w ill h ave n o e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z
rev. 1.10 1 ? 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?9 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.10 1?8 de?e??e? 1?? ?01? rev. 1.10 1 ? 9 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none
rev. 1.10 1 ? 0 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?1 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none
rev. 1.10 1?0 de?e??e? 1?? ?01? rev. 1.10 1 ? 1 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory i s r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none
rev. 1.10 1 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?? de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c
rev. 1.10 1?? de?e??e? 1?? ?01? rev. 1.10 1 ?? de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.10 1 ? 4 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?5 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu tabrd [m] read ta ble ( specifc p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( specifc p age) a ddressed b y t he t able p ointer p air (tbhp a nd t blp) i s mo ved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdc [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.10 1?4 de?e??e? 1?? ?01? rev. 1.10 1 ? 5 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to pa ckaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product t ape and reel specifcations) ? packing meterials information ? carton information
rev. 1.10 1 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?7 de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu 24 -pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ??? bsc b 0.154 bsc c 0.008 0.01 ? c 0. ? 41 bsc d 0.0 ? 9 e 0.0 ? 5 bsc f 0.004 0.010 g 0.01 ? 0.050 h 0.004 0.010 0 8 symbol dimensions in mm min. nom. max. a ? .0 bsc b ? .9 bsc c 0. ? 0 0. ? 0 c 8. ?? bsc d 1.75 e 0. ?? 5 bsc f 0.10 0. ? 5 g 0.41 1. ? 7 h 0.10 0. ? 5 0 8
rev. 1.10 1?? de?e??e? 1?? ?01? rev. 1.10 1 ? 7 de ? e ?? e ? 1 ?? ? 01 ? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu 28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ??? bsc b 0.154 bsc c 0.008 0.01 ? c 0. ? 90 bsc d 0.0 ? 9 e 0.0 ? 5 bsc f 0.004 0.0098 g 0.01 ? 0.050 h 0.004 0.010 0 8 symbol dimensions in mm min. nom. max. a ? .0 bsc b ? .9 bsc c 0. ? 0 0. ? 0 c 9.9 bsc d 1.75 e 0. ?? 5 bsc f 0.10 0. ? 5 g 0.41 1. ? 7 h 0.10 0. ? 5 0 8
rev. 1.10 1 ? 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 pb de?e??e? 1?? ?01? HT45F5R charger assp flash mcu HT45F5R charger assp flash mcu copy ? ight ? ? 01 ? ? y holtek semiconductor inc. the info ?? ation appea ? ing in this data sheet is ? elieved to ? e a ?? u ? ate at the ti ? e of pu ? li ? ation. howeve ?? holtek assu ? es no ? esponsi ? ility a ? ising f ? o ? the use of the specifcations described. the applications mentioned herein are used solely fo ? the pu ? pose of illust ? ation and holtek ? akes no wa ?? anty o ? ? ep ? esentation that su ? h appli ? ations will ? e suita ? le without fu ? the ? ? odifi ? ation ? no ? ? e ? o ?? ends the use of its p ? odu ? ts fo ? appli ? ation that ? ay p ? esent a ? isk to hu ? an life due to ? alfun ? tion o ? othe ? wise. holtek's p ? odu ? ts a ? e not autho ? ized fo ? use as ?? iti ? al ? o ? ponents in life suppo ? t devi ? es o ? syste ? s. holtek ? ese ? ves the ? ight to alte ? its products without prior notifcation. for the most up-to-date information, please visit ou ? we ? site at http://www.holtek. ? o ? .tw/en/ho ? e.

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